JPH10340978A - Mounting structure for electronic component onto wiring board - Google Patents
Mounting structure for electronic component onto wiring boardInfo
- Publication number
- JPH10340978A JPH10340978A JP15226397A JP15226397A JPH10340978A JP H10340978 A JPH10340978 A JP H10340978A JP 15226397 A JP15226397 A JP 15226397A JP 15226397 A JP15226397 A JP 15226397A JP H10340978 A JPH10340978 A JP H10340978A
- Authority
- JP
- Japan
- Prior art keywords
- organic resin
- electronic component
- wiring board
- filler
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、配線基板への電子
部品の実装構造に関し、より詳細には有機樹脂を基体と
して使用した配線基板への電子部品の実装構造に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of an electronic component on a wiring board, and more particularly to a mounting structure of an electronic component on a wiring board using an organic resin as a base.
【０００２】[0002]
【従来の技術】従来、混成集積回路装置や半導体装置等
は所定パターンの配線導体を有する配線基板上に半導体
素子や容量素子等の電子部品を搭載し、電子部品の各電
極を配線導体に接続することによって形成されている。2. Description of the Related Art Conventionally, a hybrid integrated circuit device, a semiconductor device, and the like mount electronic components such as a semiconductor element and a capacitor on a wiring board having a wiring conductor of a predetermined pattern, and connect each electrode of the electronic component to the wiring conductor. It is formed by doing.
【０００３】かかる混成集積回路装置や半導体装置等に
使用される配線基板は一般に基体として電気絶縁性に優
れた酸化アルミニウム質焼結体を基板とし、この基板の
タングステンやモリブデン等から成る配線導体を被着さ
せたものが使用されており、該タングステン等から成る
配線導体を被着させた配線基板は、このＭｏ−Ｍｎ法は
通常、タングステン、モリブデン、マンガン等の高融点
金属粉末に有機溶剤、溶媒を添加混合し、ペースト状と
なした金属ペーストを生セラミック体の外表面にスクリ
ーン印刷法により所定パターンに印刷塗布し、次にこれ
を複数枚積層するとともに還元雰囲気中で焼成し、高融
点金属粉末と生セラミツク体とを焼結一体化させる方法
である。A wiring board used for such a hybrid integrated circuit device or a semiconductor device generally uses a substrate made of an aluminum oxide sintered body having excellent electrical insulation as a substrate, and uses a wiring conductor made of tungsten, molybdenum, or the like on the substrate. The Mo-Mn method usually employs a high melting point metal powder such as tungsten, molybdenum, manganese or the like as an organic solvent for the wiring substrate on which the wiring conductor made of tungsten or the like is applied. A solvent is added and mixed, and a paste-shaped metal paste is printed and applied on the outer surface of the green ceramic body in a predetermined pattern by a screen printing method. Then, a plurality of these are laminated and fired in a reducing atmosphere to obtain a high melting point. This is a method in which the metal powder and the raw ceramic body are sintered and integrated.
【０００４】なお、前記配線導体が形成されるセラミッ
ク体としては通常、酸化アルミニウム質焼結体やムライ
ト質焼結体等の酸化物系セラミックス、或いは表面に酸
化物膜を被着させた窒化アルミニウム質焼結体や炭化珪
素質焼結体等の非酸化物系セラミックスが使用される。The ceramic body on which the wiring conductor is formed is usually an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, or an aluminum nitride having an oxide film deposited on the surface. Non-oxide ceramics such as a porous sintered body and a silicon carbide sintered body are used.
【０００５】しかしながら、このＭｏ−Ｍｎ法を用いて
配線導体を形成した場合、配線導体は金属ペーストをス
クリーン印刷することにより形成されることから微細化
が困難で、配線導体を高密度に形成することができない
という欠点を有していた。However, when the wiring conductor is formed by using the Mo-Mn method, the wiring conductor is formed by screen-printing a metal paste, so that miniaturization is difficult, and the wiring conductor is formed at a high density. Had the disadvantage of not being able to do so.
【０００６】そこで、上記欠点を解消するために配線導
体を従来周知の厚膜形成技術により形成するのに変えて
微細化が可能な薄膜形成技術を用いて高密度に形成した
多層配線基板が使用されるようになってきた。In order to solve the above-mentioned drawbacks, a multi-layer wiring board formed using a thin film forming technique capable of miniaturization instead of forming a wiring conductor by a conventionally known thick film forming technique is used. It has come to be.
【０００７】かかる配線導体を薄膜形成技術により形成
した多層配線基板は、酸化アルミニウム質焼結体から成
るセラミックスやガラス繊維を織り込んだガラス布にエ
ポキシ樹脂を含浸させて形成されるガラスエポキシ樹脂
等から成る基板の上面にスピンコート法及び熱硬化処理
によって形成されるエポキシ樹脂等の有機樹脂から成る
絶縁層と、銅やアルミニウム等の金属を無電解めっき法
や蒸着法等の薄膜形成技術及びフォトリソグラフィー技
術を採用することによって形成される薄膜の配線導体層
とを交互に多層に積層させるとともに、上下に位置する
薄膜の配線導体層を有機樹脂絶縁層に設けたスルーホー
ル導体を介して電気的に接続させた構造を有しており、
最上層の有機樹脂絶縁層上面に前記薄膜の配線導体層と
電気的に接続するボンディングパッドを形成しておき、
該ボンディングパッドに半導体素子や容量素子、抵抗器
等の電子部品の電極を半田等のロウ材を介して接続させ
るとともに最上層の有機樹脂絶縁層上面と電子部品下面
との間にエポキシ樹脂、硬化剤、充填剤等から成る有機
樹脂充填体を充填し、該有機樹脂充填体で最上層の有機
樹脂絶縁層に対する電子部品の接合強度を上げ、かつ電
子部品の電極を大気から遮断することによって多層配線
基板上に電子部品が実装される。A multilayer wiring board in which such wiring conductors are formed by a thin film forming technique is made of glass epoxy resin formed by impregnating ceramics made of aluminum oxide sintered body or glass cloth woven with glass fibers with epoxy resin. An insulating layer made of an organic resin such as an epoxy resin formed on the upper surface of a substrate by spin coating and thermosetting, and a thin film forming technique such as an electroless plating method or a vapor deposition method using a metal such as copper or aluminum, and photolithography. The thin-film wiring conductor layers formed by adopting the technology are alternately laminated in multiple layers, and the upper and lower thin-film wiring conductor layers are electrically connected through through-hole conductors provided in the organic resin insulating layer. It has a connected structure,
Forming a bonding pad electrically connected to the thin film wiring conductor layer on the uppermost organic resin insulating layer,
The electrodes of electronic components such as semiconductor elements, capacitance elements, and resistors are connected to the bonding pads via a brazing material such as solder, and an epoxy resin is cured between the upper surface of the uppermost organic resin insulating layer and the lower surface of the electronic components. By filling an organic resin filler composed of an agent, a filler, etc., increasing the bonding strength of the electronic component to the uppermost organic resin insulating layer with the organic resin filler, and shielding the electrodes of the electronic component from the atmosphere. Electronic components are mounted on the wiring board.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、この多
層配線基板への電子部品の実装においてはエポキシ樹脂
等から成る有機樹脂充填体の熱膨張係数が１０〜６０×
１０-6／℃であり、電子部品の熱膨張係数（１〜５×１
０-6／℃）と相違することから電子部品が作動時に熱を
発生し、この熱が電子部品と有機樹脂充填体に作用する
と両者間に両者の熱膨張係数の相違に起因して熱応力を
生じ、該熱応力によって電子部品と有機樹脂充填体との
接合が破れ、電子部品の実装の信頼性が大きく低下する
という欠点を招来した。However, in mounting an electronic component on this multilayer wiring board, the coefficient of thermal expansion of an organic resin filler made of epoxy resin or the like is 10 to 60 ×.
10 −6 / ° C., and the coefficient of thermal expansion of the electronic component (1 to 5 × 1
0 −6 / ° C.), the electronic component generates heat during operation, and when this heat acts on the electronic component and the organic resin filler, thermal stress occurs between the two due to the difference in the coefficient of thermal expansion between the two. And the thermal stress breaks the bond between the electronic component and the organic resin filler, resulting in a significant decrease in the reliability of mounting the electronic component.
【０００９】また上記欠点を解消するために有機樹脂充
填体中に無機物フィラーを含有させ有機樹脂充填体の熱
膨張係数を電子部品の熱膨張係数に近似させることも考
えられるが、有機樹脂充填体に無機物フィラーを含有さ
せて熱膨張係数を電子部品の熱膨張係数に近似させた場
合、今度は有機樹脂充填体と多層配線基板の有機樹脂絶
縁層との間に熱膨張係数の差が生じ、熱の印加によって
有機樹脂充填体と多層配線基板の有機樹脂絶縁層との接
合が容易に破れ、上述と同様、電子部品の実装の信頼性
が大きく低下してしまう。In order to solve the above-mentioned drawbacks, it is conceivable to include an inorganic filler in the organic resin filler to make the thermal expansion coefficient of the organic resin filler approximate to the thermal expansion coefficient of the electronic component. When the thermal expansion coefficient is approximated to the thermal expansion coefficient of the electronic component by including an inorganic filler in the resin, a difference in the thermal expansion coefficient occurs between the organic resin filler and the organic resin insulating layer of the multilayer wiring board. By the application of heat, the bonding between the organic resin filler and the organic resin insulating layer of the multilayer wiring board is easily broken, and as described above, the reliability of mounting electronic components is greatly reduced.
【００１０】本発明は上述の欠点に鑑み案出されたもの
で、その目的は配線基板及び電子部品に対して有機樹脂
充填体を強固に接合させ、実装の信頼性を高いものとし
た配線基板への電子部品の実装構造を提供することにあ
る。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to provide a wiring board in which an organic resin filler is firmly bonded to a wiring board and an electronic component, thereby improving mounting reliability. An object of the present invention is to provide a mounting structure for electronic components.
【００１１】[0011]
【課題を解決するための手段】本発明は、配線導体層を
有し、表面に前記配線導体層と電気的に接続するボンデ
ィングパッドが形成されている有機樹脂製の配線基板上
に電子部品を搭載させ、ボンディングパッドと電子部品
の下面に形成されている電極とを導電性接合部材を介し
て接続するとともに配線基板表面と少なくとも電子部品
下面との間に有機樹脂充填体を充填して成る配線基板へ
の電子部品の実装構造であって、前記有機樹脂充填体は
その内部に絶縁物フィラーが含有されており、且つ該絶
縁物フィラーの含有量が電子部品側で多く、配線基板側
で少なくなっていることを特徴とするものである。According to the present invention, there is provided an electronic component on a wiring board made of an organic resin having a wiring conductor layer and having on its surface bonding pads electrically connected to the wiring conductor layer. A wiring which is mounted, connects a bonding pad and an electrode formed on the lower surface of the electronic component through a conductive bonding member, and fills an organic resin filler between the surface of the wiring board and at least the lower surface of the electronic component. A mounting structure of an electronic component on a substrate, wherein the organic resin filler contains an insulating filler therein, and the content of the insulating filler is higher on the electronic component side and lower on the wiring substrate side. It is characterized by having become.
【００１２】また本発明は、前記有機樹脂充填体の配線
基板表面からの距離Ｔ1 における平面の有機樹脂と無機
物フィラーの面積比率Ｓ1 及び電子部品の下面から距離
Ｔ2における平面の有機樹脂と無機物フィラーの面積比
率Ｓ2 を、 Ｔ1 ＝５〜１０μｍ Ｔ2 ＝５〜１０μｍ Ｓ1 ＜Ｓ2 Ｓ1 ＝無機物フィラー面積／樹脂面積＝１／９〜３／７ Ｓ2 ＝無機物フィラー面積／樹脂面積＝３／７〜７／３ としたことを特徴とするものである。[0012] The present invention includes: the organic from the lower surface of the area ratio S 1 and the electronic components of the planar organic resin and an inorganic filler at a distance T 1 of the from the wiring board surface of the resin filling of the plane at the distance T 2 organic resin the area ratio S 2 of the inorganic filler, T 1 = 5~10μm T 2 = 5~10μm S 1 <S 2 S 1 = inorganic filler area / resin area = 1 / 9~3 / 7 S 2 = inorganic filler area / Resin area = 3/7 to 7/3.
【００１３】本発明によれば、有機樹脂製配線基板の上
面と電子部品下面との間に充填される有機樹脂充填体に
無機物フィラーを含有させるとともに該無機物フィラー
の含有量を電子部品側で多く、配線基板側で少なくした
ことから有機樹脂充填体の電子部品側は熱膨張係数が大
きくなって電子部品の熱膨張係数に近似し、また有機樹
脂充填体の配線基板側は熱膨張係数に大きな変化がなく
配線基板の熱膨張係数と近似し、これによって熱が印加
されても有機樹脂充填体と電子部品及び配線基板との接
合部に大きな熱応力が発生することはなく、有機樹脂充
填体と電子部品及び配線基板との接合を強固として電子
部品の実装の信頼性が極めて高いものとなる。According to the present invention, the organic resin filler filled between the upper surface of the organic resin wiring board and the lower surface of the electronic component contains an inorganic filler and the content of the inorganic filler is increased on the electronic component side. Because of the reduction on the wiring board side, the electronic component side of the organic resin filler has a larger thermal expansion coefficient and is close to the thermal expansion coefficient of the electronic component, and the wiring board side of the organic resin filler has a larger thermal expansion coefficient. There is no change and it is close to the thermal expansion coefficient of the wiring board, so that even if heat is applied, no large thermal stress is generated at the joint between the organic resin filler and the electronic component and the wiring board, and the organic resin filler The bonding between the electronic component and the wiring board is strengthened, and the mounting reliability of the electronic component becomes extremely high.
【００１４】[0014]
【発明の実施の形態】次に本発明を添付図面に基づき詳
細に説明する。図１は、本発明の多層配線基板の一実施
例を示し、１は基板、２は有機樹脂絶縁層、３は薄膜の
配線導体層である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a multilayer wiring board according to the present invention, wherein 1 is a substrate, 2 is an organic resin insulating layer, and 3 is a thin wiring conductor layer.
【００１５】前記基板１はその上面に有機樹脂絶縁層２
と薄膜の配線導体層３とから成る多層配線部４が配設さ
れており、該多層配線部４を支持する支持部材として作
用する。The substrate 1 has an organic resin insulating layer 2 on its upper surface.
And a multilayer wiring portion 4 composed of a thin film wiring conductor layer 3 and functions as a support member for supporting the multilayer wiring portion 4.
【００１６】前記基板１は酸化アルミニウム質焼結体や
ムライト質焼結体等の酸化物系セラミックス、或いは表
面に酸化物膜を有する窒化アルミニウム質焼結体、炭化
珪素質焼結体等の非酸化物系セラミックス、更にはガラ
ス繊維を織り込んだ布にエポキシ樹脂を含浸させたガラ
スエポキシ樹脂やガラス繊維を織り込んだ布にビスマレ
イミドトリアジン樹脂を含浸させたビスマレイミドトリ
アジン樹脂等の電気絶縁材料で形成されており、例え
ば、酸化アルミニウム質焼結体で形成されている場合に
は、アルミナ、シリカ、カルシア、マグネシア等の原料
粉末に適当な有機溶剤、溶媒を添加混合して泥漿状とな
すとともにこれを従来周知のドクターブレード法やカン
ダーロール法等を採用することによってセラミックグリ
ーンシート（セラミック生シート）を形成し、しかる
後、前記セラミックグリーンシートに適当な打ち抜き加
工を施し、所定形状となすとともに高温（約１６００
℃）で焼成することによって、或いはアルミナ等の原料
粉末に適当な有機溶剤、溶媒を添加混合して原料粉末を
調整するとともに該原料粉末をプレス成形機によって所
定形状に成形し、最後に前記成形体を約１６００℃の温
度で焼成することによって製作され、またガラスエポキ
シ樹脂から成る場合は、例えば、ガラス繊維を織り込ん
だ布にエポキシ樹脂の前駆体を含浸させるとともに該エ
ポキシ樹脂前駆体を所定の温度で熱硬化させることによ
って製作される。The substrate 1 is made of an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, or a non-oxide ceramic such as an aluminum nitride sintered body or a silicon carbide sintered body having an oxide film on its surface. Formed of oxide ceramics, and electrically insulating materials such as glass epoxy resin impregnated with epoxy resin in cloth woven with glass fiber and bismaleimide triazine resin impregnated with bismaleimide triazine resin in cloth woven with glass fiber For example, in the case of being formed of an aluminum oxide sintered body, an appropriate organic solvent and a solvent are added to a raw material powder such as alumina, silica, calcia, magnesia, etc. The ceramic green sheet (ceramics) can be obtained by adopting the well-known doctor blade method or kander roll method. Click green sheet) is formed, thereafter, subjected to a suitable punching the ceramic green sheet, a high temperature with forms with predetermined shape (approximately 1600
C) or by mixing a raw material powder such as alumina with an appropriate organic solvent and solvent to adjust the raw material powder and form the raw material powder into a predetermined shape by a press molding machine. When the body is manufactured by firing at a temperature of about 1600 ° C. and is made of a glass epoxy resin, for example, a cloth woven of glass fibers is impregnated with an epoxy resin precursor and the epoxy resin precursor is stipulated in a predetermined manner. Manufactured by thermosetting at a temperature.
【００１７】また前記基板１には上下両面に貫通する孔
径が例えば、直径３００μｍ〜５００μｍの貫通孔５が
形成されており、該貫通孔５の内壁には基板１の上下両
面に導出する導電層６が被着されている。The substrate 1 is formed with a through-hole 5 having a diameter of, for example, 300 μm to 500 μm, which penetrates the upper and lower surfaces of the substrate 1. 6 are applied.
【００１８】前記貫通孔５は後述する基板１の上面に形
成される多層配線部４の薄膜配線導体層３と外部電気回
路とを電気的に接続する、或いは基板１の上下両面に多
層配線部４を形成した場合には両面の多層配線部４の薄
膜配線導体層３同士を電気的に接続する導電層６を形成
するための形成孔として作用し、基板１にドリル孔あけ
加工法を施すことによって基板１の所定位置に所定形状
に形成される。The through hole 5 electrically connects the thin-film wiring conductor layer 3 of the multilayer wiring portion 4 formed on the upper surface of the substrate 1 to be described later and an external electric circuit. When the substrate 4 is formed, it acts as a forming hole for forming a conductive layer 6 for electrically connecting the thin film wiring conductor layers 3 of the multilayer wiring portion 4 on both surfaces, and the substrate 1 is subjected to a drilling method. Thus, a predetermined shape is formed at a predetermined position on the substrate 1.
【００１９】更に前記貫通孔５の内壁及び基板１の上下
両面には導電層６が被着形成されており、該導電層６は
例えば、銅やニッケル等の金属材料からなり、従来周知
のめっき法及びエッチング加工技術を採用することによ
って貫通孔５の内壁に両端を基板１の上下両面に導出さ
せた状態で被着形成される。Further, a conductive layer 6 is formed on the inner wall of the through hole 5 and the upper and lower surfaces of the substrate 1, and the conductive layer 6 is made of a metal material such as copper or nickel. By adopting the method and the etching technique, it is adhered to the inner wall of the through hole 5 with both ends being led out to the upper and lower surfaces of the substrate 1.
【００２０】前記導電層６は基板１の上面に形成される
多層配線部４の薄膜配線導体層３を外部電気回路に電気
的に接続したり、基板１の上下両面に形成される各々の
多層配線部４の薄膜配線導体層３同士を電気的に接続す
る作用をなす。The conductive layer 6 is used to electrically connect the thin-film wiring conductor layer 3 of the multilayer wiring portion 4 formed on the upper surface of the substrate 1 to an external electric circuit, or to form each multilayer formed on the upper and lower surfaces of the substrate 1. It functions to electrically connect the thin film wiring conductor layers 3 of the wiring portion 4 to each other.
【００２１】前記基板１にはまた上面に有機樹脂絶縁層
２と薄膜の配線導体層３とが交互に多層に積層された多
層配線部４が形成されており、かつ薄膜配線導体層３の
一部は導電層６と電気的に接続している。On the upper surface of the substrate 1, there is formed a multilayer wiring portion 4 in which an organic resin insulating layer 2 and a thin-film wiring conductor layer 3 are alternately laminated in multiple layers. The part is electrically connected to the conductive layer 6.
【００２２】前記多層配線部４を構成する有機樹脂絶縁
層２は上下に位置する薄膜配線導体層３の電気的絶縁を
図る作用をなし、薄膜配線導体層３は電気信号を伝達す
るための伝達路として作用する。The organic resin insulating layer 2 constituting the multilayer wiring section 4 functions to electrically insulate the thin film wiring conductor layer 3 located above and below, and the thin film wiring conductor layer 3 is used to transmit electric signals. Acts as a road.
【００２３】前記多層配線部４の有機樹脂絶縁層２はエ
ポキシ樹脂、ポリイミド樹脂、ビスマレイミドトリアジ
ン樹脂、ポリフェニンエーテル樹脂、ふっ素樹脂等の感
光性または熱硬化性の有機樹脂から成り、例えば感光性
のエポキシ樹脂から成る場合には、フェノールノボラッ
ク樹脂、メチロールメラミン、ジアリルジアゾニウム塩
にプロピレングリコールモノメチルエーテルアセテート
を添加混合してペースト状の感光性エポキシ樹脂前駆体
を得るととも該感光性エポキシ樹脂前駆体を基板１の上
部にスピンコート法により被着させ、しかる後、これに
高圧水銀ランプ等を用いた露光機で１０ｍＷ／ｃｍ2 〜
３０ｍＷ／ｃｍ2 のエネルギーを１．５分〜４．５分程
度照射させ、１〜３Ｊ／ｃｍ3 のエネルギーを与えるこ
とによって感光性エポキシ樹脂前駆体を光硬化させるこ
とによって形成され、また熱硬化性のエポキシ樹脂から
成る場合には、ビスフェノールＡ型エポキシ樹脂、ノボ
ラック型エポキシ樹脂、グリシジルエステル型エポキシ
樹脂等にアミン糸硬化剤、イミダゾール系硬化剤、酸無
水物系硬化剤等の硬化剤を添加混合してペースト状のエ
ポキシ樹脂前駆体を得るとともに該エポキシ樹脂前駆体
を基板１の上部にスピンコート法により被着させ、しか
る後、これを８０〜２００℃の熱で０．５〜３時間熱処
理し、熱硬化させることによって形成される。The organic resin insulating layer 2 of the multilayer wiring portion 4 is made of a photosensitive or thermosetting organic resin such as an epoxy resin, a polyimide resin, a bismaleimide triazine resin, a polyphenine ether resin, and a fluororesin. Phenol novolak resin, methylol melamine, diallyldiazonium salt and propylene glycol monomethyl ether acetate are added and mixed to obtain a paste-like photosensitive epoxy resin precursor and the photosensitive epoxy resin precursor Is applied to the upper portion of the substrate 1 by a spin coating method, and thereafter, 10 mW / cm 2 to 10 mW / cm 2 is applied by an exposure machine using a high-pressure mercury lamp or the like.
It is formed by irradiating an energy of 30 mW / cm 2 for about 1.5 minutes to 4.5 minutes and applying an energy of 1 to 3 J / cm 3 to photo-curing of the photosensitive epoxy resin precursor, and heat curing. If it is composed of epoxy resin, it is possible to add bisphenol A type epoxy resin, novolak type epoxy resin, glycidyl ester type epoxy resin, etc. with amine thread curing agent, imidazole curing agent, acid anhydride curing agent, etc. The mixture is mixed to obtain a paste-like epoxy resin precursor, and the epoxy resin precursor is applied to the upper portion of the substrate 1 by a spin coating method. Thereafter, the epoxy resin precursor is heated at 80 to 200 ° C. for 0.5 to 3 hours. It is formed by heat treatment and thermosetting.
【００２４】また前記有機樹脂絶縁層２はその各々の所
定位置に最小径が有機樹脂絶縁層２の厚みに対して約
１．５倍程度のスルーホール７が形成されており、該ス
ルーホール７は後述する有機樹脂絶縁層２を挟んで上下
に位置する薄膜配線導体層３の各々を電気的に接続する
スルーホール導体８を形成するための形成孔として作用
する。The organic resin insulating layer 2 has a through hole 7 having a minimum diameter of about 1.5 times the thickness of the organic resin insulating layer 2 at each predetermined position. Serves as a forming hole for forming a through-hole conductor 8 that electrically connects each of the thin film wiring conductor layers 3 positioned above and below the organic resin insulating layer 2 described later.
【００２５】前記有機樹脂絶縁層２に設けるスルーホー
ル７は例えば、フォトリソグラフィー技術、具体的には
有機樹脂絶縁層２上にレジスト材を塗布するとともにこ
れに露光、現像を施すことによって所定位置に所定形状
の窓部を形成し、次に前記レジスト材の窓部にエッチン
グ液を配し、レジスト材の窓部に位置する有機樹脂絶縁
層２を除去して、有機樹脂絶縁層２に穴（スルーホー
ル）を形成し、最後に前記レジスト材を有機樹脂絶縁層
２上より剥離させ除去することによって行われる。The through-hole 7 provided in the organic resin insulating layer 2 is formed at a predetermined position by, for example, photolithography, specifically, applying a resist material onto the organic resin insulating layer 2 and exposing and developing the resist material. A window having a predetermined shape is formed, and then an etchant is disposed on the window of the resist material, the organic resin insulating layer 2 located on the window of the resist material is removed, and a hole ( A through hole is formed, and finally, the resist material is peeled off from the organic resin insulating layer 2 and removed.
【００２６】更に前記各有機樹脂絶縁層２の上面には所
定パターンの薄膜配線導体層３が、また各有機樹脂絶縁
層２に設けたスルーホール７の内壁にはスルーホール導
体８が各々配設されており、スルーホール導体８によっ
て間に有機樹脂絶縁層２を挟んで上下に位置する各薄膜
配線導体層３の各々が電気的に接続されるようになって
いる。Further, a thin-film wiring conductor layer 3 having a predetermined pattern is provided on the upper surface of each organic resin insulating layer 2, and a through-hole conductor 8 is provided on the inner wall of a through hole 7 provided in each organic resin insulating layer 2. Each of the thin-film wiring conductor layers 3 located above and below the organic resin insulating layer 2 with the through-hole conductor 8 interposed therebetween is electrically connected.
【００２７】前記各有機樹脂絶縁層２の上面及びスルー
ホール７内に配設される薄膜配線導体層３及びスルーホ
ール導体８は銅、ニッケル、金、アルミニウム等の金属
材料を無電解めっき法や蒸着法、スパッタリング法等の
薄膜形成技術及びエッチング加工技術を採用することに
よって形成され、例えば、銅で形成されている場合に
は、有機樹脂絶縁層２の上面及びスルーホール７の内壁
面に硫酸銅０．０６モル／リットル、ホルマリン０．３
モル／リットル、酸化ナトリウム０．３５モル／リット
ル、エチレンジアミン四酢酸０．３５モル／リットルか
ら成る無電解銅めっき浴を用いて厚さ１μｍ乃至４０μ
ｍの銅層を被着させ、しかる後、前記銅層をエッチング
加工技術を採用することにより所定パターンに加工する
ことによって各有機樹脂絶縁層２間及び各有機樹脂絶縁
層２のスルーホール７内壁に形成される。この場合、薄
膜配線導体層３は薄膜形成技術により形成されることか
ら配線の微細化が可能であり、これによって薄膜配線導
体層３を極めて高密度に形成することが可能となる。The thin-film wiring conductor layer 3 and the through-hole conductor 8 provided on the upper surface of each of the organic resin insulating layers 2 and in the through-holes 7 are made of a metal material such as copper, nickel, gold, or aluminum by electroless plating. It is formed by adopting a thin film forming technique such as a vapor deposition method and a sputtering method and an etching technique. For example, when it is formed of copper, sulfuric acid is formed on the upper surface of the organic resin insulating layer 2 and the inner wall surface of the through hole 7. Copper 0.06 mol / l, formalin 0.3
Mol / l, 0.35 mol / l sodium oxide, 0.35 mol / l ethylenediaminetetraacetic acid using an electroless copper plating bath having a thickness of 1 μm to 40 μm.
m, and thereafter, the copper layer is processed into a predetermined pattern by employing an etching technique, whereby the inner wall of the through hole 7 between the organic resin insulating layers 2 and between the organic resin insulating layers 2 is formed. Formed. In this case, since the thin-film wiring conductor layer 3 is formed by a thin-film forming technique, the wiring can be miniaturized, thereby making it possible to form the thin-film wiring conductor layer 3 at an extremely high density.
【００２８】なお、前記有機樹脂絶縁層２と薄膜配線導
体層３とを交互に多層に積層して形成される多層配線部
４は各有機樹脂絶縁層２の上面を中心線平均粗さ（Ｒ
ａ）で０．０５μｍ≦Ｒａ≦５μｍの粗面としておく
と、有機樹脂絶縁層２上面と薄膜配線導体層３下面との
接合を強固となすことができる。従って、前記多層配線
部４の各有機樹脂絶縁層２はその上面をエッチング加工
技術等によって粗し、中心線平均粗さ（Ｒａ）で０．０
５μｍ≦Ｒａ≦５μｍの粗面としておくことが好まし
い。The multilayer wiring portion 4 formed by alternately laminating the organic resin insulating layers 2 and the thin film wiring conductor layers 3 in multiple layers has a center line average roughness (R
If a rough surface of 0.05 μm ≦ Ra ≦ 5 μm is set in a), the bonding between the upper surface of the organic resin insulating layer 2 and the lower surface of the thin film wiring conductor layer 3 can be made strong. Therefore, the upper surface of each organic resin insulating layer 2 of the multilayer wiring portion 4 is roughened by an etching technique or the like, and has a center line average roughness (Ra) of 0.0.
It is preferable to provide a rough surface of 5 μm ≦ Ra ≦ 5 μm.
【００２９】また前記有機樹脂絶縁層２はその各々の厚
みが１００μｍを超えると有機樹脂絶縁層３にフォトリ
ソグラフィー技術を採用することによってスルーホール
８を形成する際、エッチングの加工時間が長くなって、
スルーホール８を所望する鮮明な形状に形成するのが困
難となり、また５μｍ未満となると有機樹脂絶縁層２の
上面に薄膜配線導体層３との接合強度を上げるための粗
面加工を施す際、有機樹脂絶縁層２に不要な穴が形成さ
れ、上下に位置する薄膜配線導体層３に不要な電気的短
絡を招来してしまう危険性がある。従って、前記有機樹
脂絶縁層２はその各々の厚みを５μｍ〜１００μｍの範
囲としておくことが好ましい。If the thickness of each of the organic resin insulating layers 2 exceeds 100 μm, the processing time of etching becomes long when the through holes 8 are formed by employing photolithography technology in the organic resin insulating layers 3. ,
When it is difficult to form the through hole 8 into a desired clear shape, and when the thickness is less than 5 μm, when performing rough surface processing on the upper surface of the organic resin insulating layer 2 to increase the bonding strength with the thin film wiring conductor layer 3, Unnecessary holes are formed in the organic resin insulating layer 2, and there is a risk that unnecessary electrical short circuits may be caused in the thin film wiring conductor layers 3 located above and below. Therefore, it is preferable that the thickness of each of the organic resin insulating layers 2 is in the range of 5 μm to 100 μm.
【００３０】更に前記多層配線部４の各薄膜配線導体層
３はその厚みが１μｍ未満であると各薄膜配線導体層３
の電気抵抗が大きなものとなり、また４０μｍを超える
と薄膜配線導体層３を有機樹脂絶縁層２に被着させる際
に薄膜配線導体層３の内部に大きな応力が発生内在し、
該大きな内在応力によって薄膜配線導体層３が有機樹脂
絶縁層２か剥離し易いものとなる。従って、前記多層配
線部４の各薄膜配線導体層３の厚みは１μｍ乃至４０μ
ｍの範囲としておくことが好ましい。Further, if the thickness of each thin-film wiring conductor layer 3 of the multilayer wiring portion 4 is less than 1 μm, each thin-film wiring conductor layer 3
When the thickness exceeds 40 μm, a large stress is generated inside the thin-film wiring conductor layer 3 when the thin-film wiring conductor layer 3 is adhered to the organic resin insulating layer 2.
The large intrinsic stress causes the thin-film wiring conductor layer 3 to be easily separated from the organic resin insulating layer 2. Accordingly, the thickness of each thin-film wiring conductor layer 3 of the multilayer wiring portion 4 is 1 μm to 40 μm.
It is preferable to set the range of m.
【００３１】前記有機樹脂絶縁層２と薄膜配線導体層３
とを交互に多層に積層して形成される多層配線部４はそ
の最上層の有機樹脂絶縁層２ａに穴部９が形成されてお
り、該穴部９内には薄膜配線導体層３と電気的に接続し
ているボンディングパッド１０が形成されている。The organic resin insulating layer 2 and the thin film wiring conductor layer 3
The multilayer wiring portion 4 is formed by alternately laminating the thin film wiring conductor layer 3 with the thin film wiring conductor layer 3 in the uppermost organic resin insulating layer 2a. Bonding pads 10 are formed which are connected to each other.
【００３２】前記最上層の有機樹脂絶縁層２に形成され
ている穴部９は薄膜配線導体層３に電気的接続をもつボ
ンディングパッド１０を形成するための形成穴として作
用し、最上層の有機樹脂絶縁層２ａに従来周知のフォト
リソグラフィー技術を採用することによって所定位置に
所定の開口径に形成される。The hole 9 formed in the uppermost organic resin insulating layer 2 functions as a forming hole for forming a bonding pad 10 having electrical connection to the thin film wiring conductor layer 3, The resin insulating layer 2a is formed at a predetermined position with a predetermined opening diameter by employing a conventionally known photolithography technique.
【００３３】また前記最上層の有機樹脂絶縁層２ａに設
けた穴部９内に形成されるボンディングパッド１０は半
導体素子や容量素子、抵抗器等の電子部品Ａの電極を薄
膜配線導体層３に電気的に接続させる作用をなし、前記
薄膜配線導体層３と同じ金属材料、具体的には銅、ニッ
ケル、金、アルミニウム等の金属材料から成り、薄膜配
線導体層３を形成するのと同様の方法によって最上層の
有機樹脂絶縁層２ａに設けた穴部９内に薄膜配線導体層
３と電気的接続をもって形成される。The bonding pads 10 formed in the holes 9 provided in the uppermost organic resin insulating layer 2a are used to connect the electrodes of the electronic component A such as semiconductor elements, capacitance elements and resistors to the thin film wiring conductor layer 3. The thin-film wiring conductor layer 3 is electrically connected and made of the same metal material as the thin-film wiring conductor layer 3, specifically, a metal material such as copper, nickel, gold, or aluminum. It is formed in the hole 9 provided in the uppermost organic resin insulating layer 2a by a method and electrically connected to the thin film wiring conductor layer 3.
【００３４】更に前記最上層の有機樹脂絶縁層２ａに設
けた穴部９内に形成されているボンディングパッド１０
には電子部品Ａの下面に形成された電極ａが半田等のロ
ウ材１１を介して接続され、かつ最上層の有機樹脂絶縁
層２ａと電子部品Ａの下面との間には有機樹脂充填体１
２が充填される。Further, the bonding pad 10 formed in the hole 9 provided in the uppermost organic resin insulating layer 2a is formed.
An electrode a formed on the lower surface of the electronic component A is connected via a brazing material 11 such as solder, and an organic resin filler is provided between the uppermost organic resin insulating layer 2a and the lower surface of the electronic component A. 1
2 are filled.
【００３５】前記有機樹脂充填体１２は最上層の有機樹
脂絶縁層２ａと電子部品Ａとを強固に接合させ、電子部
品Ａの実装強度を強いものにするとともに電子部品Ａの
電極ａ等を大気より遮断し、電極ａ等が腐蝕を受け断線
したりするのを防止する作用をなす。The organic resin filler 12 firmly joins the uppermost organic resin insulating layer 2a and the electronic component A to increase the mounting strength of the electronic component A and to reduce the electrodes a of the electronic component A to the atmosphere. It further functions to prevent the electrodes a and the like from being corroded and disconnected.
【００３６】前記有機樹脂充填体１２はエポキシ樹脂等
から成り、エポキシ樹脂等の樹脂前駆体を最上層の有機
樹脂絶縁層２ａと電子部品Ａの下面との間に充填すると
ともにこれを１３０℃〜１７０℃の温度で熱硬化させる
ことによって形成される。The organic resin filler 12 is made of an epoxy resin or the like, and is filled with a resin precursor such as an epoxy resin between the uppermost organic resin insulating layer 2a and the lower surface of the electronic component A. It is formed by thermosetting at a temperature of 170 ° C.
【００３７】また前記有機樹脂充填体１２はその内部に
結晶性シリカ、溶融シリカ、アルミナ等から成る無機物
フィラーが、電子部品Ａ側は多く、最上層の有機樹脂絶
縁層２ａは少なく含有されている。The organic resin filler 12 contains therein an inorganic filler made of crystalline silica, fused silica, alumina, etc., on the side of the electronic component A, and less in the uppermost organic resin insulating layer 2a. .
【００３８】前記無機物フィラーは有機樹脂充填体１２
の熱膨張係数を制御するとともに有機樹脂充填体１２の
耐湿性、誘電特性等を向上させる作用をなし、有機樹脂
充填体１２の電子部品Ａ側における含有量を多くしたこ
とからこの領域の熱膨張係数は１０×１０-6／℃程度と
なって電子部品Ａの熱膨張係数（１〜５×１０-6／℃）
に近似し、また最上層の有機樹脂絶縁層２ａ側における
含有量は少なくしたことからこの領域の熱膨張係数は４
０〜６０×１０-6／℃程度となって最上層の有機樹脂絶
縁層２ａの熱膨張係数（４０〜８０×１０-6／℃）に近
似することとなり、これによって熱が印加されても有機
樹脂充填体１２と電子部品Ａ及び最上層の有機樹脂絶縁
層２ａとの接合部に大きな熱応力が発生することはな
く、有機樹脂充填体１２と電子部品Ａ及び最上層の有機
樹脂絶縁層２ａとの接合を強固として電子部品Ａの実装
の信頼性が極めて高いものとなる。The inorganic filler is an organic resin filler 12
Has the effect of controlling the coefficient of thermal expansion of the organic resin filler 12 and improving the moisture resistance and dielectric properties of the organic resin filler 12 and increasing the content of the organic resin filler 12 on the electronic component A side. The coefficient is about 10 × 10 −6 / ° C., and the coefficient of thermal expansion of the electronic component A (1 to 5 × 10 −6 / ° C.)
, And the content on the side of the uppermost organic resin insulating layer 2a was reduced, so that the thermal expansion coefficient of this region was 4%.
The thermal expansion coefficient is about 0 to 60 × 10 −6 / ° C., which is close to the coefficient of thermal expansion (40 to 80 × 10 −6 / ° C.) of the uppermost organic resin insulating layer 2a. A large thermal stress does not occur at the joint between the organic resin filler 12 and the electronic component A and the uppermost organic resin insulating layer 2a, and the organic resin filler 12 and the electronic component A and the uppermost organic resin insulating layer The reliability of mounting the electronic component A becomes extremely high by strengthening the bonding with 2a.
【００３９】なお、前記無機物フィラーの有機樹脂充填
体１２への含有は、最上層の有機樹脂絶縁層２ａから５
〜１０μｍ離れた位置における平面の有機樹脂と無機物
フィラーの面積比率Ｓ1 と電子部品Ａから５〜１０μｍ
離れた位置における平面の有機樹脂と無機物フィラーの
面積比率Ｓ2 が、Ｓ1 ＜Ｓ2 、Ｓ1 ＝無機物フィラー面
積／樹脂面積＝１／９〜３／７、Ｓ2 ＝無機物フィラー
面積／樹脂面積＝３／７〜７／３となったとき有機樹脂
充填体１２と最上層の有機樹脂絶縁層２ａ及び電子部品
Ａとの各々の間に発生する熱応力を極めて小さいものと
なし、これによって有機樹脂充填体１２と電子部品Ａ及
び最上層の有機樹脂絶縁層２ａとの接合を強固として電
子部品Ａの実装の信頼性が極めて高いものとなすことが
できる。The content of the inorganic filler in the organic resin filler 12 depends on whether the uppermost organic resin insulating layer 2a
10 to 10 μm apart from the area ratio S 1 of the organic resin and the inorganic filler in the plane at a position separated from the electronic component A by 5 to 10 μm
The area ratio S 2 between the organic resin and the inorganic filler in a plane at a distant position is S 1 <S 2 , S 1 = inorganic filler area / resin area = 1/9 to 3/7, S 2 = inorganic filler area / resin When the area = 3/7 to 7/3, the thermal stress generated between the organic resin filler 12 and each of the uppermost organic resin insulating layer 2a and the electronic component A is made extremely small. The bonding between the organic resin filler 12 and the electronic component A and the uppermost organic resin insulating layer 2a is strengthened, and the mounting reliability of the electronic component A can be extremely high.
【００４０】従って、前記無機物フィラーの有機樹脂充
填体１２への含有は、最上層の有機樹脂絶縁層２ａから
５〜１０μｍ離れた位置における平面の有機樹脂と無機
物フィラーの面積比率Ｓ1 と電子部品Ａから５〜１０μ
ｍ離れた位置における平面の有機樹脂と無機物フィラー
の面積比率Ｓ2 が、Ｓ1 ＜Ｓ2 、Ｓ1 ＝無機物フィラー
面積／樹脂面積＝１／９〜３／７、Ｓ2 ＝無機物フィラ
ー面積／樹脂面積＝３／７〜７／３となるようにしてお
くことが好ましい。Accordingly, the content of the inorganic filler in the organic resin filler 12 depends on the area ratio S 1 of the flat organic resin and the inorganic filler at a position 5 to 10 μm away from the uppermost organic resin insulating layer 2 a and the electronic component. 5 to 10μ from A
The area ratio S 2 between the organic resin and the inorganic filler in a plane at a distance of m is S 1 <S 2 , S 1 = inorganic filler area / resin area = 1/9 to 3/7, and S 2 = inorganic filler area / It is preferable that the resin area is 3/7 to 7/3.
【００４１】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば、上述の実施例におい
ては基板１の上面のみに有機樹脂絶縁層２と薄膜の配線
導体層３とから成る多層配線部４を設け、この多層配線
部に形成したボンディングパッド１０に電子部品Ａを実
装したが、多層配線部４を基板１の下面側のみに設けて
も、上下の両面に設けてもよい。It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. A multilayer wiring portion 4 comprising an organic resin insulating layer 2 and a thin-film wiring conductor layer 3 was provided only on the upper surface, and an electronic component A was mounted on a bonding pad 10 formed on the multilayer wiring portion. 1 may be provided only on the lower surface side, or may be provided on both upper and lower surfaces.
【００４２】[0042]
【発明の効果】本発明によれば、有機樹脂製配線基板の
上面と電子部品下面との間に充填される有機樹脂充填体
に無機物フィラーを含有させるとともに該無機物フィラ
ーの含有量を電子部品側で多く、配線基板側で少なくし
たことから有機樹脂充填体の電子部品側は熱膨張係数が
大きくなって電子部品の熱膨張係数に近似し、また有機
樹脂充填体の配線基板側は熱膨張係数に大きな変化がな
く配線基板の熱膨張係数と近似し、これによって熱が印
加されても有機樹脂充填体と電子部品及び配線基板との
接合部に大きな熱応力が発生することはなく、有機樹脂
充填体と電子部品及び配線基板との接合を強固として電
子部品の実装の信頼性が極めて高いものとなる。According to the present invention, the organic resin filler filled between the upper surface of the organic resin wiring board and the lower surface of the electronic component contains an inorganic filler, and the content of the inorganic filler is reduced on the electronic component side. The thermal expansion coefficient on the electronic component side of the organic resin filler is large and approximates the thermal expansion coefficient of the electronic component, and the thermal expansion coefficient on the wiring substrate side of the organic resin filler is small. There is no significant change in the thermal expansion coefficient of the wiring board, and the thermal expansion coefficient is similar to that of the wiring board. Even when heat is applied, no large thermal stress is generated at the joint between the organic resin filler and the electronic component and the wiring board. The bonding between the filler and the electronic component and the wiring board is strengthened, and the mounting reliability of the electronic component is extremely high.
【図１】本発明の配線基板への電子部品の実装構造を説
明するための一実施例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment for describing a mounting structure of an electronic component on a wiring board according to the present invention.
１・・・・・・・・・基板 ２・・・・・・・・・有機樹脂絶縁層 ３・・・・・・・・・薄膜配線導体層 ４・・・・・・・・・多層配線部 ８・・・・・・・・・スルーホール導体 １０・・・・・・・・ボンディングパッド １１・・・・・・・・ロウ材 １２・・・・・・・・有機樹脂充填体 Ａ・・・・・・・・・電子部品 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Organic resin insulating layer 3 ... Thin film wiring conductor layer 4 ... Multilayer Wiring part 8: Through-hole conductor 10: Bonding pad 11: Brazing material 12: Organic resin filler A: Electronic parts
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０５Ｋ 1/18 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification code FI H05K 1/18
Claims (2)
と電気的に接続するボンディングパッドが形成されてい
る有機樹脂製の配線基板上に電子部品を搭載させ、ボン
ディングパッドと電子部品の下面に形成されている電極
とを導電性接合部材を介して接続するとともに配線基板
表面と少なくとも電子部品下面との間に有機樹脂充填体
を充填して成る配線基板への電子部品の実装構造であっ
て、前記有機樹脂充填体はその内部に絶縁物フィラーが
含有されており、且つ該絶縁物フィラーの含有量が電子
部品側で多く、配線基板側で少なくなっていることを特
徴とする配線基板への電子部品の実装構造。An electronic component is mounted on a wiring board made of an organic resin having a wiring conductor layer and having on its surface bonding pads electrically connected to the wiring conductor layer. Mounting structure of an electronic component on a wiring board, wherein an electrode formed on the lower surface of the electronic component is connected via a conductive bonding member and an organic resin filler is filled between the surface of the wiring substrate and at least the lower surface of the electronic component. Wherein the organic resin filler contains an insulating filler therein, and the content of the insulating filler is higher on the electronic component side and lower on the wiring board side. The mounting structure of electronic components on a wiring board.
距離Ｔ1 における平面の有機樹脂と無機物フィラーの面
積比率Ｓ1 及び電子部品の下面から距離Ｔ2 における平
面の有機樹脂と無機物フィラーの面積比率Ｓ2 が下記条
件を満足する請求項１記載の配線基板への電子部品の実
装構造。 Ｔ1 ＝５〜１０μｍ Ｔ2 ＝５〜１０μｍ Ｓ1 ＜Ｓ2 Ｓ1 ＝無機物フィラー面積／樹脂面積＝１／９〜３／７ Ｓ2 ＝無機物フィラー面積／樹脂面積＝３／７〜７／３2. The area ratio S 1 of the organic resin and the inorganic filler in a plane at a distance T 1 from the surface of the wiring board of the organic resin filler and the ratio of the organic resin and the inorganic filler in a plane at a distance T 2 from the lower surface of the electronic component. 2. The structure for mounting an electronic component on a wiring board according to claim 1, wherein the area ratio S2 satisfies the following condition. T 1 = 5 to 10 μm T 2 = 5 to 10 μm S 1 <S 2 S 1 = inorganic filler area / resin area = 1/9 to 3/7 S 2 = inorganic filler area / resin area = 3/7 to 7 / 3
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15226397A JPH10340978A (en) | 1997-06-10 | 1997-06-10 | Mounting structure for electronic component onto wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15226397A JPH10340978A (en) | 1997-06-10 | 1997-06-10 | Mounting structure for electronic component onto wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10340978A true JPH10340978A (en) | 1998-12-22 |
Family
ID=15536675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15226397A Pending JPH10340978A (en) | 1997-06-10 | 1997-06-10 | Mounting structure for electronic component onto wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10340978A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001244638A (en) * | 1999-12-20 | 2001-09-07 | Matsushita Electric Ind Co Ltd | Module with built-in circuit and its manufacturing method |
| JP2003078006A (en) * | 2001-09-04 | 2003-03-14 | Ibiden Co Ltd | Semiconductor chip and method of manufacturing the same |
| JP2006512775A (en) * | 2003-01-02 | 2006-04-13 | クリー インコーポレイテッド | Semiconductor device manufacturing method and flip-chip integrated circuit |
| JP2011171650A (en) * | 2010-02-22 | 2011-09-01 | Kyocera Corp | Circuit board |
| US8569970B2 (en) | 2007-07-17 | 2013-10-29 | Cree, Inc. | LED with integrated constant current driver |
-
1997
- 1997-06-10 JP JP15226397A patent/JPH10340978A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001244638A (en) * | 1999-12-20 | 2001-09-07 | Matsushita Electric Ind Co Ltd | Module with built-in circuit and its manufacturing method |
| JP2003078006A (en) * | 2001-09-04 | 2003-03-14 | Ibiden Co Ltd | Semiconductor chip and method of manufacturing the same |
| JP2006512775A (en) * | 2003-01-02 | 2006-04-13 | クリー インコーポレイテッド | Semiconductor device manufacturing method and flip-chip integrated circuit |
| US8569970B2 (en) | 2007-07-17 | 2013-10-29 | Cree, Inc. | LED with integrated constant current driver |
| US8810151B2 (en) | 2007-07-17 | 2014-08-19 | Cree, Inc. | LED with integrated constant current driver |
| JP2011171650A (en) * | 2010-02-22 | 2011-09-01 | Kyocera Corp | Circuit board |
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