JPH11186434A - Multi-layer wiring substrate - Google Patents
Multi-layer wiring substrateInfo
- Publication number
- JPH11186434A JPH11186434A JP34911797A JP34911797A JPH11186434A JP H11186434 A JPH11186434 A JP H11186434A JP 34911797 A JP34911797 A JP 34911797A JP 34911797 A JP34911797 A JP 34911797A JP H11186434 A JPH11186434 A JP H11186434A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- organic resin
- resin insulating
- insulating layer
- wiring conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、多層配線基板に関
し、より詳細には混成集積回路装置や半導体素子を収容
する半導体素子収納用パッケージ等に使用される多層配
線基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board used for a hybrid integrated circuit device, a semiconductor element housing package for housing a semiconductor element, and the like.
【０００２】[0002]
【従来の技術】従来、混成集積回路装置や半導体素子収
納用パッケージ等に使用される多層配線基板はその配線
導体がＭｏ−Ｍｎ法等の厚膜形成技術によって形成され
ている。2. Description of the Related Art Hitherto, a multilayer wiring board used in a hybrid integrated circuit device, a package for accommodating a semiconductor element, or the like, has its wiring conductor formed by a thick film forming technique such as the Mo-Mn method.
【０００３】このＭｏ−Ｍｎ法は通常、タングステン、
モリブデン、マンガン等の高融点金属粉末に有機溶剤、
溶媒を添加混合し、ペースト状となした金属ペーストを
生セラミック体の外表面にスクリーン印刷法により所定
パターンに印刷塗布し、次にこれを複数枚積層するとと
もに還元雰囲気中で焼成し、高融点金属粉末と生セラミ
ック体とを焼結一体化させる方法である。[0003] This Mo-Mn method is generally used for tungsten,
Organic solvents for high melting point metal powders such as molybdenum and manganese,
A solvent is added and mixed, and a paste-shaped metal paste is printed and applied on the outer surface of the green ceramic body in a predetermined pattern by a screen printing method. Then, a plurality of these are laminated and fired in a reducing atmosphere to obtain a high melting point. This is a method of sintering and integrating a metal powder and a green ceramic body.
【０００４】なお、前記配線導体が形成されるセラミッ
ク体としては、通常酸化アルミニウム質焼結体やムライ
ト質焼結体等の酸化物系セラミックス、或いは表面に酸
化物膜を被着させた窒化アルミニウム質焼結体や炭化珪
素質焼結体等の非酸化物系セラミックスが使用される。The ceramic body on which the wiring conductor is formed is usually an oxide-based ceramic such as an aluminum oxide sintered body or a mullite sintered body, or aluminum nitride having an oxide film deposited on the surface. Non-oxide ceramics such as a porous sintered body and a silicon carbide sintered body are used.
【０００５】しかしながら、このＭｏ−Ｍｎ法を用いて
配線導体を形成した場合、配線導体は金属ペーストをス
クリーン印刷することにより形成されることから微細化
が困難で配線導体を高密度に形成することができないと
いう欠点を有していた。However, when the wiring conductor is formed by using the Mo-Mn method, the wiring conductor is formed by screen-printing a metal paste. Had the drawback that it could not be done.
【０００６】そこで上記欠点を解消するために配線導体
を従来周知の厚膜形成技術により形成するのに変えて微
細化が可能な薄膜形成技術を用いて高密度に形成した多
層配線基板が採用されるようになってきた。In order to solve the above-mentioned drawbacks, a multilayer wiring board has been adopted in which a wiring conductor is formed at a high density by using a thin film forming technique capable of miniaturization instead of forming the wiring conductor by a conventionally known thick film forming technique. It has become.
【０００７】かかる配線導体を薄膜形成技術により形成
した多層配線基板は、酸化アルミニウム質焼結体から成
るセラミックスやガラス繊維を織り込んだガラス布にエ
ポキシ樹脂を含浸させて形成されるガラスエポキシ樹脂
等から成る基板の上面にスピンコート法及び熱硬化処理
によって形成されるエポキシ樹脂等の有機樹脂から成る
絶縁層と、銅やアルミニウム等の金属を無電解メッキ法
や蒸着法等の薄膜形成技術及びフォトリソグラフィー技
術を採用することによって形成される薄膜配線導体層と
を交互に積層させたるとともに、上下に位置する薄膜配
線導体層を有機樹脂絶縁層に設けたスルーホール導体を
介して電気的に接続させた構造を有しており、最上層の
有機樹脂絶縁層上面に前記薄膜配線導体層と電気的に接
続するボンディングパッドを形成しておき、該ボンディ
ングパッドに半導体素子等の能動部品や容量素子、抵抗
器等の受動部品の電極を熱圧着等により接続させるよう
になっている。A multilayer wiring board in which such wiring conductors are formed by a thin film forming technique is made of glass epoxy resin formed by impregnating ceramics made of aluminum oxide sintered body or glass cloth woven with glass fibers with epoxy resin. An insulating layer made of an organic resin such as an epoxy resin formed by spin coating and thermosetting on the upper surface of a substrate made of a metal, such as copper or aluminum, and a thin film forming technique such as an electroless plating method or a vapor deposition method, and photolithography. The thin-film wiring conductor layers formed by adopting the technology were alternately laminated, and the thin-film wiring conductor layers positioned above and below were electrically connected via through-hole conductors provided in the organic resin insulating layer. A bond having a structure and electrically connected to the thin film wiring conductor layer on the upper surface of the uppermost organic resin insulating layer. Previously formed pads have become active component, a capacitor such as a semiconductor element to said bonding pad, a passive component of the electrode of the resistor or the like so as to be connected by thermocompression bonding or the like.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、この有
機樹脂絶縁層と薄膜配線導体層を交互に積層して成る多
層配線基板は、最上層の有機樹脂絶縁層上面に形成した
ボンディングパッドに半導体素子等の能動部品や容量素
子、抵抗器等の受動部品の電極を熱圧着等により接続さ
せる際、最上層の有機樹脂絶縁層にへこみが発生して、
ボンディングパッドに半導体素子等の能動部品や容量素
子、抵抗器等の受動部品の電極を確実、強固に接続させ
ることができないという欠点を有していた。However, a multi-layer wiring board comprising the organic resin insulating layers and the thin film wiring conductor layers alternately laminated is provided with bonding elements formed on the upper surface of the uppermost organic resin insulating layer, such as semiconductor elements. When connecting the electrodes of passive components such as active components, capacitive elements and resistors by thermocompression bonding, dents occur in the uppermost organic resin insulating layer,
There has been a drawback that electrodes of active components such as semiconductor devices and the like and capacitance components and passive components such as resistors and the like cannot be securely and firmly connected to the bonding pads.
【０００９】本発明は上述の欠点に鑑み案出されたもの
で、その目的は配線導体を薄膜形成技術により形成し、
配線導体を高密度に形成するのを可能とするとともに、
配線導体に半導体素子や容量素子等の電極を確実、強固
に電気的接続させることができる多層配線基板を提供す
ることにある。The present invention has been made in view of the above-mentioned drawbacks, and has as its object to form a wiring conductor by a thin film forming technique,
While making it possible to form wiring conductors at high density,
An object of the present invention is to provide a multilayer wiring board that can securely and firmly electrically connect electrodes of a semiconductor element, a capacitor element, and the like to a wiring conductor.
【００１０】[0010]
【課題を解決するための手段】本発明は、基板上に、有
機樹脂絶縁層と薄膜配線導体とを交互に積層するととも
に上下に位置する薄膜配線導体を有機樹脂絶縁層に設け
たスルーホール導体を介して電気的に接続してなり、最
上層の有機樹脂絶縁層上面に、前記薄膜配線導体と電気
的に接続し、外部の電子部品が接続されるボンディング
パッドを設けて成る多層配線基板であって、前記ボンデ
ィングパッドの表面にＣｏ、Ｔａ、Ｍｏ、Ｗ、Ｐｄ、Ｐ
ｔの少なくとも一種から成る被覆層を被着させたことを
特徴とするものである。According to the present invention, there is provided a through-hole conductor in which an organic resin insulating layer and a thin film wiring conductor are alternately laminated on a substrate and thin film wiring conductors located above and below are provided on the organic resin insulating layer. And a bonding pad electrically connected to the thin film wiring conductor on the upper surface of the uppermost organic resin insulating layer and provided with bonding pads to which external electronic components are connected. Then, Co, Ta, Mo, W, Pd, P
a coating layer comprising at least one of t.
【００１１】また本発明は前記被覆層の厚みが３μｍ乃
至１０μｍであることを特徴とするものである。Further, the present invention is characterized in that the thickness of the coating layer is 3 μm to 10 μm.
【００１２】本発明の多層配線基板によれば、絶縁基板
上に薄膜形成技術によって配線を形成したことから配線
の微細化が可能となり、配線を極めて高密度に形成する
ことが可能となる。According to the multilayer wiring board of the present invention, since the wiring is formed on the insulating substrate by the thin film forming technique, the wiring can be miniaturized, and the wiring can be formed at an extremely high density.
【００１３】また本発明の多層基板によれば、ボンディ
ングパッドの表面にＣｏ、Ｔａ、Ｍｏ、Ｗ、Ｐｄ、Ｐｔ
等から成る硬質で、良導性で、且つ半導体素子等の電極
と接合しやすい金属材料の被覆層を被着させたことか
ら、ボンディングパッドに半導体素子等の能動部品や容
量素子、抵抗器等の受動部品の電極を熱圧着等により接
続させる際、最上層の有機樹脂絶縁層にへこみが形成さ
れるのが前記被覆層の配設によって有効に阻止され、そ
の結果、ボンディングパッドに半導体素子等の能動部品
や容量素子、抵抗器等の受動部品の電極を確実、強固に
電気的接続させることが可能となる。Further, according to the multilayer substrate of the present invention, Co, Ta, Mo, W, Pd, Pt
Since a coating layer made of a metal material that is hard, has good conductivity, and is easily bonded to an electrode of a semiconductor element or the like, is applied to the bonding pad, active components such as a semiconductor element, a capacitance element, a resistor, etc. When the electrodes of the passive components are connected by thermocompression bonding or the like, the formation of a dent in the uppermost organic resin insulating layer is effectively prevented by the provision of the coating layer. The electrodes of passive components such as active components, capacitive elements, and resistors can be reliably and firmly electrically connected.
【００１４】[0014]
【発明の実施の形態】次に、本発明を添付図面に基づき
詳細に説明する。図１は、本発明の多層配線基板の一実
施例を示し、１は基板、２は有機樹脂絶縁層、３は薄膜
配線導体層である。Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a multilayer wiring board according to the present invention, wherein 1 is a substrate, 2 is an organic resin insulating layer, and 3 is a thin-film wiring conductor layer.
【００１５】前記基板１はその上面に有機樹脂絶縁層２
と薄膜配線導体層３とからなる多層配線部４が配設され
ており、該多層配線部４を支持する支持部材として作用
する。The substrate 1 has an organic resin insulating layer 2 on its upper surface.
And a thin-film wiring conductor layer 3, and a multilayer wiring portion 4 is provided, and functions as a support member for supporting the multilayer wiring portion 4.
【００１６】前記基板１は酸化アルミニウム質焼結体や
ムライト質焼結体等の酸化物系セラミックス、或いは表
面に酸化物膜を有する窒化アルミニウム質焼結体や炭化
珪素質焼結体等の非酸化物系セラミックス、更にはガラ
ス繊維を織り込んだ布にエポキシ樹脂を含浸させたガラ
スエポキシ樹脂等の電気絶縁材料で形成されており、例
えば、酸化アルミニウム質焼結体で形成されている場合
には、酸化アルミニウム、酸化珪素、酸化マグネシウ
ム、酸化カルシウム等の粉末原料に適当な有機溶剤、溶
媒を添加混合して泥漿状となすとともにこれを従来周知
のドクターブレード法やカレンダーロール法を採用する
ことによってセラミックグリーンシート（セラミック生
シート）を形成し、しかる後、前記セラミックグリーン
シートに適当な打ち抜き加工を施し、所定形状となすと
ともに高温（約１６００℃）で焼成することによって、
或いは酸化アルミニウム等の原料粉末に適当な有機溶
剤、溶媒を添加混合して原料粉末を調整するとともに該
原料粉末をプレス成型機によって所定形状に成形し、最
後に前記成形体を約１６００℃の温度で焼成することに
よって製作され、またガラスエポキシ樹脂からなる場合
には、例えば、ガラス繊維を織り込んだ布にエポキシ樹
脂の前駆体を含浸させるとともに該エポキシ樹脂前駆体
を所定の温度で熱硬化させることによって製作される。The substrate 1 is made of an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, or a non-conductive body such as an aluminum nitride sintered body or a silicon carbide sintered body having an oxide film on the surface. Oxide ceramics, and further made of an electrically insulating material such as glass epoxy resin impregnated with epoxy resin in a cloth woven with glass fiber, for example, when formed of aluminum oxide sintered body By adding an appropriate organic solvent and a solvent to powder materials such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide, and mixing them to form a slurry, and employing a conventionally known doctor blade method or calendar roll method, A ceramic green sheet (ceramic green sheet) is formed, and then a suitable punch is formed on the ceramic green sheet. By baking at a high temperature (about 1600 ° C.) with can process the applied and forms a predetermined shape,
Alternatively, an appropriate organic solvent and a solvent are added to and mixed with a raw material powder such as aluminum oxide to prepare the raw material powder, and at the same time, the raw material powder is formed into a predetermined shape by a press molding machine. In the case of being manufactured by baking with, and made of glass epoxy resin, for example, impregnating an epoxy resin precursor into a cloth woven of glass fiber and thermally curing the epoxy resin precursor at a predetermined temperature Produced by
【００１７】また、前記基板１はその上面に有機樹脂絶
縁層２と薄膜配線導体層３とが交互に多層に積層されて
形成される多層配線部４が被着されており、該多層配線
部４を構成する有機樹脂絶縁層２は上下に位置する薄膜
配線導体層３の電気的絶縁をはかる作用をなし、また薄
膜配線導体層３は電気信号を伝達するための伝達路とし
て作用する。The substrate 1 has a multilayer wiring portion 4 formed by alternately laminating an organic resin insulating layer 2 and a thin film wiring conductor layer 3 on the upper surface thereof. The organic resin insulating layer 2 constituting 4 functions to electrically insulate the thin film wiring conductor layers 3 positioned above and below, and the thin film wiring conductor layer 3 functions as a transmission path for transmitting an electric signal.
【００１８】前記多層配線部４の有機樹脂絶縁層２は、
エポキシ樹脂、ビスマレイミドトリアジン樹脂、ポリフ
ェニレンエーテル樹脂、フッ素樹脂当の有機樹脂から成
り、例えば、エポキシ樹脂からなる場合、ビスフェノー
ルＡ型エポキシ樹脂、ノボラック型エポキシ樹脂、グリ
シジルエステル型エポキシ樹脂等にアミン系硬化剤、イ
ミダゾール系硬化剤、酸無水物系硬化剤等の硬化剤を添
加混合してペースト状のエポキシ樹脂前駆体を得るとと
もに該エポキシ樹脂前駆体を基板１の上部にスピンコー
ト法により被着させ、しかる後、これを８０℃〜２００
℃の熱で０．５〜３時間熱処理し、熱硬化させることに
よって形成させる。The organic resin insulating layer 2 of the multilayer wiring section 4
An epoxy resin, a bismaleimide triazine resin, a polyphenylene ether resin, or an organic resin such as a fluororesin. For example, when an epoxy resin is used, amine-based curing is performed on a bisphenol A type epoxy resin, a novolak type epoxy resin, a glycidyl ester type epoxy resin, or the like. And a curing agent such as an imidazole-based curing agent and an acid anhydride-based curing agent are added and mixed to obtain a paste-like epoxy resin precursor, and the epoxy resin precursor is applied to the upper portion of the substrate 1 by spin coating. After that, this is brought to 80 ° C. to 200 ° C.
The film is formed by heat-treating with heat of 0.5 ° C. for 0.5 to 3 hours and heat-curing.
【００１９】更に前記多層配線部４の有機樹脂絶縁層２
はその各々の所定位置に最小径が有機樹脂絶縁層２の厚
みに対して約１．５倍程度のスルーホール５が形成され
ており、該スルーホール５は後述する有機樹脂絶縁層２
を介して上下に位置する薄膜配線導体層３の各々を電気
的に接続するスルーホール導体６を形成するための形成
孔として作用する。Furthermore, the organic resin insulating layer 2 of the multilayer wiring section 4
Has a through hole 5 having a minimum diameter of about 1.5 times the thickness of the organic resin insulating layer 2 at each predetermined position.
And acts as a forming hole for forming a through-hole conductor 6 that electrically connects each of the thin film wiring conductor layers 3 located above and below via the through hole.
【００２０】前記有機樹脂絶縁層２に設けるスルーホー
ル５は有機樹脂絶縁層２に従来周知のフォトリソグラフ
ィー技術を採用することによって所定の径に形成され
る。The through hole 5 provided in the organic resin insulating layer 2 is formed in the organic resin insulating layer 2 to a predetermined diameter by employing a conventionally known photolithography technique.
【００２１】また前記各有機樹脂絶縁層２の上面には所
定パターンの薄膜配線導体層３が、更に各有機樹脂絶縁
層２に設けたスルーホール５の内壁にはスルーホール導
体６が各々配設されており、スルーホール導体６によっ
て間に有機樹脂絶縁層２を挟んで上下に位置する各薄膜
配線導体層３の各々が電気的に接続されるようになって
いる。A thin-film wiring conductor layer 3 having a predetermined pattern is provided on the upper surface of each organic resin insulating layer 2, and a through-hole conductor 6 is provided on the inner wall of a through hole 5 provided in each organic resin insulating layer 2. The respective through-hole conductors 6 electrically connect the respective thin-film wiring conductor layers 3 positioned above and below the organic resin insulating layer 2 therebetween.
【００２２】前記各有機樹脂絶縁層２の上面及びスルー
ホール５の内壁に配設される薄膜配線導体層３及びスル
ーホール導体層６は銅、アルミニウム等の金属材料を無
電解メッキ法や蒸着法、スパッタリング法等の薄膜形成
技術及びフォトリソグラフィー技術を採用することによ
って形成され、例えば、銅で形成されている場合には、
有機樹脂絶縁層２の上面及びスルーホール５の内表面
に、硫酸銅０．０６モル／リットル、ホルマリン０．３
モル／リットル、水酸化ナトリウム０．３５モル／リッ
トル、エチレンジアミン四酢酸０．３５モル／リットル
から成る無電解銅メッキ浴を用いて厚さ１μｍ乃至４０
μｍの銅を被着させ、しかる後、前記銅層をフォトリソ
グラフィー技術により所定パターンに加工することによ
って各有機樹脂絶縁層２間、及びスルーホール５内壁に
配設される。この場合、薄膜配線導体層３及びスルーホ
ール導体６は薄膜形成技術により形成されることから配
線の微細化が可能であり、これによって薄膜配線導体層
３を極めて高密度に形成することが可能となる。The thin film wiring conductor layer 3 and the through hole conductor layer 6 disposed on the upper surface of each organic resin insulating layer 2 and the inner wall of the through hole 5 are made of a metal material such as copper or aluminum by electroless plating or vapor deposition. , Formed by employing a thin film forming technology such as a sputtering method and a photolithography technology, for example, when formed of copper,
On the upper surface of the organic resin insulating layer 2 and the inner surface of the through hole 5, copper sulfate 0.06 mol / l, formalin 0.3
Mol / l, sodium hydroxide 0.35 mol / l, and ethylenediaminetetraacetic acid 0.35 mol / l using an electroless copper plating bath having a thickness of 1 μm to 40 μm.
A copper layer having a thickness of μm is deposited, and then the copper layer is processed into a predetermined pattern by a photolithography technique to be disposed between the organic resin insulating layers 2 and on the inner wall of the through hole 5. In this case, since the thin-film wiring conductor layer 3 and the through-hole conductor 6 are formed by a thin-film forming technique, the wiring can be miniaturized, thereby making it possible to form the thin-film wiring conductor layer 3 at an extremely high density. Become.
【００２３】なお、前記有機樹脂絶縁層２と薄膜配線導
体層３とを交互に多層に配設して形成される多層配線部
４は各有機樹脂絶縁層２の上面を中心線平均粗さ（Ｒ
ａ）で０．０５μｍ≦Ｒａ≦５μｍの粗面としておくと
有機樹脂絶縁層２と薄膜配線導体層３との接合及び上下
に位置する有機樹脂絶縁層２同士の接合を強固となすこ
とができる。従って、前記多層配線部４の各有機樹脂絶
縁層２はその上面をエッチング加工法等によって粗し、
中心線平均粗さ（Ｒａ）で０．０５μｍ≦Ｒａ≦５μｍ
の粗面としておくことが好ましい。The multilayer wiring portion 4 formed by alternately arranging the organic resin insulating layers 2 and the thin film wiring conductor layers 3 in multiple layers has a center line average roughness (top surface) of each organic resin insulating layer 2. R
By setting a rough surface of 0.05 μm ≦ Ra ≦ 5 μm in a), the bonding between the organic resin insulating layer 2 and the thin-film wiring conductor layer 3 and the bonding between the organic resin insulating layers 2 located above and below can be made strong. . Therefore, the upper surface of each organic resin insulating layer 2 of the multilayer wiring portion 4 is roughened by an etching method or the like,
Center line average roughness (Ra): 0.05 μm ≦ Ra ≦ 5 μm
It is preferable to make the surface rough.
【００２４】また前記有機樹脂絶縁層２はその各々の厚
みが１００μｍを超えると有機樹脂絶縁層２にフォトリ
ソグラフィー技術を採用することによってスルーホール
５を形成する際、エッチング加工時間が長くなってスル
ーホール５を所望する鮮明な形状に形成するのが困難と
なり、また５μｍ未満となると有機樹脂絶縁層２の上面
に上下に位置する有機樹脂絶縁層２の接合強度を上げる
ための粗面加工を施す際、有機樹脂絶縁層２に不要な穴
が形成され、上下に位置する薄膜配線導体層３に不要な
電気的短絡を招来してしまう危険性がある。従って、前
記有機樹脂絶縁層２はその各々の厚みを５μｍ乃至１０
０μｍの範囲としておくことが好ましい。If the thickness of each of the organic resin insulating layers 2 exceeds 100 μm, the photolithography technique is used to form the through holes 5 in the organic resin insulating layers 2, so that the etching processing time becomes longer and the through-holes become longer. It is difficult to form the hole 5 into a desired clear shape, and if it is less than 5 μm, rough surface processing is performed on the upper surface of the organic resin insulating layer 2 to increase the bonding strength of the upper and lower organic resin insulating layers 2. In this case, unnecessary holes are formed in the organic resin insulating layer 2, and there is a risk that unnecessary electrical short circuits may be caused in the thin film wiring conductor layers 3 located above and below. Accordingly, the organic resin insulating layer 2 has a thickness of 5 μm to 10 μm.
It is preferable to set the range to 0 μm.
【００２５】更に、前記多層配線部４の各薄膜配線導体
層３はその厚みが１μｍ未満となると各薄膜配線導体層
３の電気抵抗が大きなものとなって各薄膜配線導体層３
に所定の電気信号を伝達させることが困難なものとな
り、また４０μｍを超えると薄膜配線導体層３を有機樹
脂絶縁層２に被着させる際に薄膜配線導体層３内に大き
な応力が発生内在し、該大きな内在応力によって薄膜配
線導体層３が有機樹脂絶縁層２より剥離し易いものとな
る。従って、前記多層配線部４の各薄膜配線導体層３の
厚みは１μｍ乃至４０μｍの範囲としておくことが好ま
しい。Further, when the thickness of each thin-film wiring conductor layer 3 of the multilayer wiring portion 4 is less than 1 μm, the electric resistance of each thin-film wiring conductor layer 3 becomes large and each thin-film wiring conductor layer 3 becomes large.
When the thickness exceeds 40 μm, a large stress is generated in the thin-film wiring conductor layer 3 when the thin-film wiring conductor layer 3 is applied to the organic resin insulating layer 2. The large intrinsic stress causes the thin-film wiring conductor layer 3 to be easily separated from the organic resin insulating layer 2. Therefore, it is preferable that the thickness of each thin-film wiring conductor layer 3 of the multilayer wiring portion 4 be in the range of 1 μm to 40 μm.
【００２６】前記有機樹脂絶縁層２と薄膜配線導体層３
とを交互に多層に配設して形成される多層配線部４は更
に、最上層の有機樹脂絶縁層２ａの上面に薄膜配線導体
層３と電気的に接続しているボンディングパッド７が、
また前記ボンディングパッド７の表面には金属材料から
成る被覆層８が被着されている。The organic resin insulating layer 2 and the thin-film wiring conductor layer 3
Are formed alternately in multiple layers, and the bonding pad 7 electrically connected to the thin film wiring conductor layer 3 is further formed on the upper surface of the uppermost organic resin insulating layer 2a.
The surface of the bonding pad 7 is covered with a coating layer 8 made of a metal material.
【００２７】前記ボンディングパッド７は、半導体素子
等の能動部品や容量素子、抵抗器等の受動部品の電極が
熱圧着等によって接続され、これによって半導体素子等
の能動部品や容量素子、抵抗器等の受動部品が薄膜配線
導体層３に電気的に接続されることとなる。The bonding pad 7 is connected to electrodes of active components such as semiconductor elements, capacitors, and passive components such as resistors by thermocompression bonding or the like, whereby active components such as semiconductor elements, capacitors, resistors, etc. are connected. Are electrically connected to the thin-film wiring conductor layer 3.
【００２８】前記ボンディングパッド７は、薄膜配線導
体層３と同じ金属材料、具体的には銅、アルミニウム等
の金属材料から成り、最上層の有機樹脂絶縁層２ａ上に
薄膜配線導体層３を形成する際に同時に前記薄膜配線導
体層３と電気的接続をもって形成される。The bonding pad 7 is made of the same metal material as the thin film wiring conductor layer 3, specifically, a metal material such as copper or aluminum. The thin film wiring conductor layer 3 is formed on the uppermost organic resin insulating layer 2a. At the same time, the thin film wiring conductor layer 3 is formed with electrical connection.
【００２９】また、前記ボンディングパッド７の表面に
はＣｏ、Ｔａ、Ｍｏ、Ｗ、Ｐｄ、Ｐｔ等の金属材料から
成る被覆層８が被着されており、該Ｃｏ、Ｔａ、Ｍｏ、
Ｗ、Ｐｄ、Ｐｔ等の金属から成る被覆層８は硬質で外力
印加によって変形しにくいことからボンディングパッド
７に半導体素子等の能動部品や容量素子、抵抗器等の受
動部品の電極を熱圧着等により接続させる際、最上層の
有機樹脂絶縁層２ａにへこみが形成されることはほとん
ど無く、これによってボンディングパッド７に半導体素
子等の能動部品や容量素子、抵抗器等の受動部品の電極
が熱圧着等によって確実、強固に電気的接続されること
となる。A coating layer 8 made of a metal material such as Co, Ta, Mo, W, Pd, or Pt is adhered on the surface of the bonding pad 7.
Since the coating layer 8 made of a metal such as W, Pd, or Pt is hard and hard to be deformed by application of an external force, the electrodes of active components such as a semiconductor device, electrodes of a capacitive device, and passive components such as a resistor are thermally pressed on the bonding pad 7. When the connection is made, the dent is scarcely formed in the uppermost organic resin insulating layer 2a, so that the electrodes of active components such as a semiconductor element, electrodes of a capacitive element, and passive components such as a resistor are thermally attached to the bonding pad 7. The electrical connection is reliably and firmly made by crimping or the like.
【００３０】また前記Ｃｏ、Ｔａ、Ｍｏ、Ｗ、Ｐｄ、Ｐ
ｔ等の金属材料は比抵抗が１１×１０-6Ω・ｃｍ以下で
良導電性であることからボンディングパッド７に半導体
素子等の能動部品や容量素子、抵抗器等の受動部品の電
極を接続させた場合、被覆層８がボンディングパッド７
と半導体素子等との電気的接続を阻害することはなく、
両者を極めて良好に電気的接続することができる。The Co, Ta, Mo, W, Pd, P
Since the metal material such as t has a specific resistance of 11 × 10 −6 Ω · cm or less and has good conductivity, the electrodes of active components such as semiconductor elements and electrodes of passive components such as capacitors and resistors are connected to the bonding pad 7. In this case, the covering layer 8 is
Without interrupting the electrical connection between the
Both can be very well electrically connected.
【００３１】更に前記Ｃｏ、Ｔａ、Ｍｏ、Ｗ、Ｐｄ、Ｐ
ｔ等の金属材料は表面酸化しにくく表面状態が安定して
いることからボンディングパッド７に半導体素子等の電
極を熱圧着等により接続させる際、被覆層８がボンディ
ングパッド７と半導体素子等の能動部品や容量素子、抵
抗器等の受動部品の電極との接続を阻害することもな
く、両者を極めて確実、強固に電気的接続することがで
きる。Further, the Co, Ta, Mo, W, Pd, P
Since a metal material such as t is hardly oxidized on the surface and has a stable surface state, when an electrode of a semiconductor element or the like is connected to the bonding pad 7 by thermocompression bonding or the like, the covering layer 8 forms an active layer between the bonding pad 7 and the semiconductor element or the like. Both of them can be very reliably and firmly electrically connected without obstructing the connection with the electrodes of passive components such as components, capacitive elements, resistors and the like.
【００３２】前記被覆層８はＣｏ、Ｔａ、Ｍｏ、Ｗ、Ｐ
ｄ、Ｐｔ等をめっき法やスパッタ法、蒸着法等の技術を
使用することによってボンディングパッド７の表面に被
着される。The coating layer 8 is made of Co, Ta, Mo, W, P
d, Pt, and the like are applied to the surface of the bonding pad 7 by using a technique such as a plating method, a sputtering method, and an evaporation method.
【００３３】前記被覆層８はまたその厚みが３μｍ未満
となるとボンディングパッド７に半導体素子等の能動部
品や容量素子、抵抗器等の受動部品の電極を熱圧着等に
より接続させる際、最上層の有機樹脂絶縁層２ａにへこ
みが発生して、ボンディングパッド７に半導体素子等の
能動部品や容量素子、抵抗器等の受動部品の電極を確
実、強固に接続させることが困難となる傾向にあり、ま
た１０μｍを超えると被覆層８を形成する際、被覆層８
の内部に大きな応力が発生内在して被覆層８とボンディ
ングパッド７との密着力が劣化し、両者間に剥離等を招
来する危険性がある。従って、前記被覆層８はその厚み
を３μｍ乃至１０μｍの範囲にしておくことが好まし
い。When the thickness of the coating layer 8 is less than 3 μm, when the electrodes of active components such as semiconductor elements and electrodes of passive components such as capacitors and resistors are connected to the bonding pads 7 by thermocompression or the like, the uppermost layer is formed. Dent is generated in the organic resin insulating layer 2a, and it tends to be difficult to securely and firmly connect electrodes of active components such as semiconductor elements, capacitance elements, and passive components such as resistors to the bonding pad 7, When the thickness exceeds 10 μm, when forming the coating layer 8,
There is a danger that a large stress will be generated inside and the adhesion between the coating layer 8 and the bonding pad 7 will be deteriorated, and separation or the like will be caused between them. Therefore, it is preferable that the thickness of the coating layer 8 be in the range of 3 μm to 10 μm.
【００３４】かくして、本発明の多層配線基板によれ
ば、最上層の有機樹脂絶縁層２ａ表面に設けたボンディ
ングパッド７に半導体素子等の能動部品や容量素子、抵
抗器等の受動部品を接続させることによって半導体装置
や混成集積回路装置となり、薄膜配線導体層３の一部を
外部電気回路に接続させれば前記半導体素子や容量素子
等が外部電気回路に電気的に接続されることとなる。Thus, according to the multilayer wiring board of the present invention, active components such as semiconductor devices and passive components such as capacitance devices and resistors are connected to the bonding pads 7 provided on the surface of the uppermost organic resin insulating layer 2a. As a result, a semiconductor device or a hybrid integrated circuit device is formed. If a part of the thin film wiring conductor layer 3 is connected to an external electric circuit, the semiconductor element, the capacitor, and the like are electrically connected to the external electric circuit.
【００３５】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば、上述の実施例におい
ては基板１の上面のみに有機樹脂絶縁層２と薄膜配線導
体層３とを交互に積層して形成される多層配線部４を被
着させたが、多層配線部４を基板１の下面側のみに設け
ても、上下の両主面に設けてもよい。It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. Although the multilayer wiring portion 4 formed by alternately laminating the organic resin insulating layers 2 and the thin film wiring conductor layers 3 is applied only on the upper surface, the multilayer wiring portion 4 may be provided only on the lower surface side of the substrate 1. , On both upper and lower main surfaces.
【００３６】[0036]
【発明の効果】本発明の多層配線基板によれば、絶縁基
板上に薄膜形成技術によって配線を形成したことから配
線の微細化が可能となり、配線を極めて高密度に形成す
ることが可能となる。According to the multilayer wiring board of the present invention, since the wiring is formed on the insulating substrate by the thin film forming technique, the wiring can be miniaturized and the wiring can be formed at an extremely high density. .
【００３７】また本発明の多層基板によれば、ボンディ
ングパッドの表面にＣｏ、Ｔａ、Ｍｏ、Ｗ、Ｐｄ、Ｐｔ
等から成る硬質で、良導性で、且つ半導体素子等の電極
と接合しやすい金属材料の被覆層を被着させたことか
ら、ボンディングパッドに半導体素子等の能動部品や容
量素子、抵抗器等の受動部品の電極を熱圧着等により接
続させる際、最上層の有機樹脂絶縁層にへこみが形成さ
れるのが前記被覆層の配設によって有効に阻止され、そ
の結果、ボンディングパッドに半導体素子等の能動部品
や容量素子、抵抗器等の受動部品の電極を確実、強固に
電気的接続させることが可能となる。Further, according to the multilayer substrate of the present invention, Co, Ta, Mo, W, Pd, Pt
Since a coating layer made of a metal material that is hard, has good conductivity, and is easily bonded to an electrode of a semiconductor element or the like, is applied to the bonding pad, active components such as a semiconductor element, a capacitance element, a resistor, etc. When the electrodes of the passive components are connected by thermocompression bonding or the like, the formation of a dent in the uppermost organic resin insulating layer is effectively prevented by the provision of the coating layer. The electrodes of passive components such as active components, capacitive elements, and resistors can be reliably and firmly electrically connected.
【図１】本発明の多層配線基板の一実施例を示す部分拡
大図面である。FIG. 1 is a partially enlarged view showing one embodiment of a multilayer wiring board of the present invention.
１・・・・基板 ２・・・・有機樹脂絶縁層 ２ａ・・・最上層の有機樹脂絶縁層 ３・・・・薄膜配線導体層 ４・・・・多層配線部 ６・・・・スルーホール導体 ７・・・・ボンディングパッド ８・・・・被覆層 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Organic resin insulation layer 2a ... Top organic resin insulation layer 3 ... Thin film wiring conductor layer 4 ... Multilayer wiring part 6 ... Through hole Conductor 7 ··· Bonding pad 8 ··· Coating layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０５Ｋ 3/46 Ｈ０５Ｋ 3/46 Ｓ Ｈ０１Ｌ 23/14 Ｍ // Ｈ０１Ｌ 21/60 21/92 ６０３Ｆ ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification symbol FI H05K 3/46 H05K 3/46 S H01L 23/14 M // H01L 21/60 21/92 603F
Claims (2)
層とを交互に積層するとともに上下に位置する薄膜配線
導体層を有機樹脂絶縁層に設けたスルーホール導体を介
して電気的に接続してなり、最上層の有機樹脂絶縁層上
面に、前記薄膜配線導体層と電気的に接続し、外部の電
子部品が接続されるボンディングパッドを設けて成る多
層配線基板であって、前記ボンディングパッドの表面に
Ｃｏ、Ｔａ、Ｍｏ、Ｗ、Ｐｄ、Ｐｔの少なくとも一種か
ら成る被覆層を被着させたことを特徴とする多層配線基
板。An organic resin insulating layer and a thin-film wiring conductor layer are alternately laminated on a substrate, and electrically connected via a through-hole conductor provided on the upper and lower thin-film wiring conductor layers in the organic resin insulating layer. A multi-layer wiring board comprising: a bonding pad electrically connected to the thin-film wiring conductor layer and connected to an external electronic component on an upper surface of an uppermost organic resin insulating layer; A multilayer wiring board, wherein a coating layer made of at least one of Co, Ta, Mo, W, Pd, and Pt is applied to a surface of a pad.
あることを特徴とする請求項１に記載の多層配線基板。2. The multilayer wiring board according to claim 1, wherein said coating layer has a thickness of 3 μm to 10 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34911797A JPH11186434A (en) | 1997-12-18 | 1997-12-18 | Multi-layer wiring substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34911797A JPH11186434A (en) | 1997-12-18 | 1997-12-18 | Multi-layer wiring substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11186434A true JPH11186434A (en) | 1999-07-09 |
Family
ID=18401612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34911797A Pending JPH11186434A (en) | 1997-12-18 | 1997-12-18 | Multi-layer wiring substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11186434A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6803302B2 (en) | 1999-11-22 | 2004-10-12 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device having a mechanically robust pad interface |
| CN100382263C (en) * | 2004-03-05 | 2008-04-16 | 沈育浓 | Semiconductor wafer device having multilayer wiring structure and packaging method thereof |
-
1997
- 1997-12-18 JP JP34911797A patent/JPH11186434A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6803302B2 (en) | 1999-11-22 | 2004-10-12 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device having a mechanically robust pad interface |
| US7169694B2 (en) | 1999-11-22 | 2007-01-30 | Freescale Semiconductor, Inc. | Method for forming a bond pad interface |
| CN100382263C (en) * | 2004-03-05 | 2008-04-16 | 沈育浓 | Semiconductor wafer device having multilayer wiring structure and packaging method thereof |
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