JPH10322030A - Multilayered wiring board - Google Patents

Multilayered wiring board

Info

Publication number
JPH10322030A
JPH10322030A JP9132153A JP13215397A JPH10322030A JP H10322030 A JPH10322030 A JP H10322030A JP 9132153 A JP9132153 A JP 9132153A JP 13215397 A JP13215397 A JP 13215397A JP H10322030 A JPH10322030 A JP H10322030A
Authority
JP
Japan
Prior art keywords
layer
organic resin
resin insulating
thin film
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9132153A
Other languages
Japanese (ja)
Inventor
Akira Yoshimoto
亮 吉本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP9132153A priority Critical patent/JPH10322030A/en
Publication of JPH10322030A publication Critical patent/JPH10322030A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered wiring board where the electrodes of active parts such as a semiconductor element, etc., or passive elements such as a capacitive element, a resistor, etc., can be electrically connected securely and firmly to bonding pads, by forming a part of wiring conductors by a thin film formation technology, and enabling the wiring conductors to be formed in high density, and effectively preventing a warp from occurring at large. SOLUTION: This board is constituted by stacking organic resin insulating layers 2 and thin film wiring conductor layers 3 alternately on at least one main surface of the insulating board 1 where conductive layers 6 are made inside and on the surface, and electrically connecting the thin film wiring conductors 3 positioned above and below with each other through a through hole conductor 10 provided in the organic resin insulating layer 2, and this is constituted by providing itself with a bonding pad which electrically connects with the thin film wiring conductor layer 3 and to which an outside electric part A is connected, on the topside of the uppermost organic resin insulating layer 2. In this case, for the insulating board 1, a frame-shaped metallic layer 7b is burned to surround the conductive layer 6 made within the insulating board 1, in its inside and besides at the periphery.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、多層配線基板に関
し、より詳細には混成集積回路装置や半導体素子を収容
する半導体素子収納用パッケージ等に使用される多層配
線基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board used for a hybrid integrated circuit device, a semiconductor element housing package for housing a semiconductor element, and the like.

【０００２】[0002]

【従来の技術】従来、混成集積回路装置や半導体素子収
納用パッケージ等に使用される多層配線基板はその配線
導体がＭｏ−Ｍｎ法等の厚膜形成技術によって形成され
ている。2. Description of the Related Art Hitherto, a multilayer wiring board used in a hybrid integrated circuit device, a package for accommodating a semiconductor element, or the like, has its wiring conductor formed by a thick film forming technique such as the Mo-Mn method.

【０００３】このＭｏ−Ｍｎ法は通常、タングステン、
モリブデン、マンガン等の高融点金属粉末に有機溶剤、
溶媒を添加混合し、ペースト状となした金属ペーストを
生セラミック体の外表面にスクリーン印刷法により所定
パターンに印刷塗布し、次ぎにこれを複数枚積層すると
ともに還元雰囲気中で焼成し、高融点金属粉末と生セラ
ミック体とを焼結一体化させる方法である。[0003] This Mo-Mn method is generally used for tungsten,
Organic solvents for high melting point metal powders such as molybdenum and manganese,
A solvent is added and mixed, and a paste-like metal paste is applied by printing on the outer surface of the green ceramic body in a predetermined pattern by a screen printing method. Then, a plurality of these layers are laminated and fired in a reducing atmosphere to obtain a high melting point. This is a method of sintering and integrating a metal powder and a green ceramic body.

【０００４】なお、前記配線導体が形成されるセラミッ
ク体としては通常、酸化アルミニウム質焼結体やムライ
ト質焼結体等の酸化物系セラミックス、或いは表面に酸
化物膜を被着させた窒化アルミニウム質焼結体や炭化珪
素質焼結体等の非酸化物系セラミックスが使用される。The ceramic body on which the wiring conductor is formed is usually an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, or an aluminum nitride having an oxide film deposited on the surface. Non-oxide ceramics such as a porous sintered body and a silicon carbide sintered body are used.

【０００５】しかしながら、このＭｏ−Ｍｎ法を用いて
配線導体を形成した場合、配線導体は金属ペーストをス
クリーン印刷することにより形成されることから微細化
が困難で配線導体を高密度に形成することができないと
いう欠点を有していた。However, when the wiring conductor is formed by using the Mo-Mn method, the wiring conductor is formed by screen-printing a metal paste. Had the drawback that it could not be done.

【０００６】そこで上記欠点を解消するために配線導体
の一部を従来の厚膜形成技術で形成するのに変えて微細
化が可能な薄膜形成技術を用いて高密度に形成した多層
配線基板が使用されるようになってきた。In order to solve the above-mentioned drawbacks, a multilayer wiring board formed at a high density by using a thin film forming technique capable of miniaturization instead of forming a part of the wiring conductor by the conventional thick film forming technique has been proposed. It has come to be used.

【０００７】かかる配線導体の一部を薄膜形成技術によ
り形成した多層配線基板は、ビスマレイミドトリアジン
樹脂やガラス繊維を織り込んだ布にエポキシ樹脂を含浸
させて形成されるガラスエポキシ樹脂等から成り、内部
及び表面に導電層を有する絶縁基板と、該絶縁基板の上
面にスピンコート法及び熱硬化処理等によって形成され
るエポキシ樹脂からなる有機樹脂絶縁層と、銅やアルミ
ニウム等の金属をめっき法や蒸着法等の薄膜形成技術及
びフォトリソグラフィー技術を採用することによって形
成される薄膜配線導体層とを交互に積層させるととも
に、上下に位置する薄膜配線導体層を有機樹脂絶縁層に
設けたスルーホールの内壁に被着させたスルーホール導
体を介して電気的に接続させた構造を有しており、最上
層の有機樹脂絶縁層上面に、前記薄膜配線導体層と電気
的に接続するボンディングパッドを形成しておき、該ボ
ンディングパッドに半導体素子等の能動部品や容量素
子、抵抗器等の受動部品の電極を熱圧着等により接続さ
せるようになっている。A multilayer wiring board in which a part of such a wiring conductor is formed by a thin film forming technique is made of a glass epoxy resin formed by impregnating a bismaleimide triazine resin or a cloth woven with glass fibers with an epoxy resin, and the like. And an insulating substrate having a conductive layer on the surface, an organic resin insulating layer made of an epoxy resin formed on the upper surface of the insulating substrate by a spin coating method, a thermosetting treatment, or the like, and a metal such as copper or aluminum plated or deposited by metal. The thin film wiring conductor layers formed by adopting the thin film forming technology such as the photolithography technology and the thin film wiring conductor layer are alternately laminated, and the upper and lower thin film wiring conductor layers are provided in the organic resin insulating layer. Has a structure in which it is electrically connected via a through-hole conductor adhered to the uppermost organic resin insulating layer. A bonding pad electrically connected to the thin-film wiring conductor layer is formed on the surface, and electrodes of active components such as semiconductor elements and electrodes of passive components such as capacitors and resistors are connected to the bonding pads by thermocompression bonding or the like. It is made to let.

【０００８】なお、この多層配線基板においては、絶縁
基板の内部及び表面に形成した導電層と薄膜配線導体層
の一部とが電気的に接続しており、絶縁基板に形成した
導電層を外部電気回路に電気的に接続することによって
最上層の有機樹脂絶縁層上面に形成したボンディングパ
ッドに接続されている半導体素子等の能動部品や容量素
子、抵抗器等の受動部品はその電極が薄膜配線導体及び
導電層を介して外部電気回路に電気的に接続されること
となる。In this multilayer wiring board, the conductive layer formed inside and on the surface of the insulating substrate and a part of the thin film wiring conductive layer are electrically connected, and the conductive layer formed on the insulating substrate is connected to the outside. Electrodes of active components such as semiconductor devices and passive components such as capacitors and resistors connected to the bonding pads formed on the uppermost organic resin insulating layer by electrical connection to the electric circuit are thin film wiring. It is electrically connected to an external electric circuit via the conductor and the conductive layer.

【０００９】[0009]

【発明が解決しようとする課題】しかしながら、この有
機樹脂絶縁層と薄膜配線導体層とを交互に多層に積層し
て形成される多層配線基板は、絶縁基板の上面に有機樹
脂絶縁層を形成する際、絶縁基板に有機樹脂絶縁層の熱
硬化時に発生する応力が作用して絶縁基板に大きな反り
を発生させてしまい、その結果、絶縁基板の上面に形成
されている有機樹脂絶縁層表面のボンディングパッドの
形成位置にばらつきが生じ、ボンディングパッドに半導
体素子等の能動部品や容量素子、抵抗器等の受動部品の
電極を確実、強固に電気的接続することができないとい
う欠点を招来した。However, in a multilayer wiring board formed by alternately laminating the organic resin insulating layers and the thin film wiring conductor layers in a multilayer, the organic resin insulating layer is formed on the upper surface of the insulating substrate. At this time, the stress generated during the thermal curing of the organic resin insulating layer acts on the insulating substrate, causing a large warpage of the insulating substrate, and as a result, bonding of the surface of the organic resin insulating layer formed on the upper surface of the insulating substrate. Variations occur in the positions where the pads are formed, resulting in a drawback that the electrodes of active components such as semiconductor elements and the like and capacitors and passive components such as resistors cannot be reliably and electrically connected to the bonding pads.

【００１０】本発明は上述の欠点に鑑み案出されたもの
で、その目的は配線導体の一部を薄膜形成技術により形
成し、配線導体を高密度に形成するのを可能とするとと
もに全体に反りが発生するのを有効に防止し、ボンディ
ングパッドに半導体素子等の能動部品や容量素子、抵抗
器等の受動部品の電極を確実、強固に電気的接続するこ
とができる多層配線基板を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to form a part of a wiring conductor by a thin film forming technique so that the wiring conductor can be formed at a high density and the whole can be formed. Provided is a multilayer wiring board capable of effectively preventing warpage from occurring and reliably and firmly electrically connecting electrodes of active components such as semiconductor devices and electrodes of passive components such as capacitors and resistors to bonding pads. It is in.

【００１１】[0011]

【課題を解決するための手段】本発明は、内部及び表面
に導電層が形成されている絶縁基板の少なくとも一主面
上に、有機樹脂絶縁層と薄膜配線導体層とを交互に積層
するとともに上下に位置する薄膜配線導体層を有機樹脂
絶縁層に設けたスルーホール導体を介して電気的に接続
して成り、最上層の有機樹脂絶縁層上面に、前記薄膜配
線導体層と電気的に接続し、外部の電子部品が接続され
るボンディングパッドを設けて成る多層配線基板であっ
て、前記絶縁基板はその内部で、かつ外周部に、絶縁基
板内部に形成されている導電層を取り囲むように枠状の
金属層が埋設されていることを特徴とするものである。According to the present invention, an organic resin insulating layer and a thin-film wiring conductor layer are alternately laminated on at least one principal surface of an insulating substrate having a conductive layer formed inside and on the surface. The upper and lower thin film wiring conductor layers are electrically connected to each other through a through-hole conductor provided in the organic resin insulating layer, and are electrically connected to the thin film wiring conductor layer on the uppermost organic resin insulating layer. A multi-layer wiring board provided with bonding pads to which external electronic components are connected, wherein the insulating substrate surrounds a conductive layer formed inside and at an outer peripheral portion thereof. A frame-shaped metal layer is embedded.

【００１２】本発明の多層配線基板によれば、絶縁基板
上に薄膜形成技術によって配線の一部を形成したことか
ら配線の微細化が可能となり、従来に比べて配線を極め
て高密度に形成することが可能となる。According to the multilayer wiring board of the present invention, since a part of the wiring is formed on the insulating substrate by the thin film forming technique, the wiring can be miniaturized, and the wiring can be formed at an extremely high density as compared with the related art. It becomes possible.

【００１３】また本発明の多層配線基板によれば、内部
及び表面に導電層が形成されている絶縁基板の内部で、
かつ外周部に、絶縁基板内部に形成されている導電層を
取り囲むようにして枠状の金属層を埋設させたことから
絶縁基板の反りに対する強度が増大し、絶縁基板上に有
機樹脂絶縁層を形成する際、絶縁基板に有機樹脂絶縁層
の熱硬化時に発生する応力が作用したとしても絶縁基板
に大きな反りが発生することは殆どなく、その結果、ボ
ンディングパッドの形成位置が同一の平面となり、ボン
ディングパッドに半導体素子等の能動部品や容量素子、
抵抗器等の受動部品の電極を確実、且つ強固に電気的接
続することが可能となる。Further, according to the multilayer wiring board of the present invention, the inside of the insulating substrate having the conductive layer formed inside and on the surface thereof,
In addition, since the frame-shaped metal layer is buried in the outer peripheral portion so as to surround the conductive layer formed inside the insulating substrate, the strength against warpage of the insulating substrate increases, and the organic resin insulating layer is formed on the insulating substrate. At the time of formation, even if stress generated at the time of thermal curing of the organic resin insulating layer acts on the insulating substrate, there is almost no occurrence of large warpage in the insulating substrate, and as a result, the formation positions of the bonding pads are on the same plane, Active components such as semiconductor elements and capacitive elements on bonding pads,
Electrodes of passive components such as resistors can be reliably and firmly electrically connected.

【００１４】[0014]

【発明の実施の形態】次に、本発明を添付図面に基づき
詳細に説明する。図１は、本発明の多層配線基板の一実
施例を示し、１は絶縁基板、２は有機樹脂絶縁層、３は
薄膜配線導体層である。Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a multilayer wiring board according to the present invention, wherein 1 is an insulating substrate, 2 is an organic resin insulating layer, and 3 is a thin-film wiring conductor layer.

【００１５】前記絶縁基板１はその上面に有機樹脂絶縁
層２と薄膜配線導体３とから成る多層配線部４が配設さ
れており、該多層配線部４を支持する支持部材として作
用する。On the upper surface of the insulating substrate 1, a multilayer wiring portion 4 comprising an organic resin insulating layer 2 and a thin film wiring conductor 3 is disposed, and functions as a support member for supporting the multilayer wiring portion 4.

【００１６】前記絶縁基板１はガラス繊維を織り込んだ
布にエポキシ樹脂を含浸させたガラスエポキシ樹脂基板
やガラス繊維を織り込んだ布にビスマレイミドトリアジ
ン樹脂を含浸させたビスマレイミドトリアジン基板等の
電気絶縁基板を複数枚積層するとともにその各々を一体
的に接合させて形成されており、例えば、ガラスエポキ
シ樹脂基板を使用して形成する場合は、ガラス繊維を織
り込んだ布にエポキシ樹脂の前駆体を含浸させたものを
複数枚積層し、しかる後、前記エポキシ樹脂前駆体を１
００℃〜２００℃の温度で熱硬化させることによって製
作される。The insulating substrate 1 is an electrically insulating substrate such as a glass epoxy resin substrate obtained by impregnating an epoxy resin into a cloth woven with glass fibers or a bismaleimide triazine substrate obtained by impregnating a bismaleimide triazine resin into a cloth woven with glass fibers. It is formed by laminating a plurality of sheets and joining each of them integrally.For example, when forming using a glass epoxy resin substrate, impregnating a cloth woven with glass fibers with a precursor of epoxy resin. The epoxy resin precursor is then laminated with a plurality of
It is manufactured by thermosetting at a temperature of 00C to 200C.

【００１７】また前記絶縁基板１には上下両面に貫通す
る孔径が例えば、直径０．３ｍｍ〜０．５ｍｍの貫通孔
５が絶縁基板１にドリル孔あけ加工法等を施すことによ
って形成されており、かつ絶縁基板１の内部、上下両面
及び貫通孔５の内壁には銅やアルミニウム、銀、ニッケ
ル等の金属材料から成る導電層６が被着形成されてい
る。The insulating substrate 1 is formed with a through hole 5 having a diameter of, for example, 0.3 mm to 0.5 mm, which penetrates the upper and lower surfaces of the insulating substrate 1 by subjecting the insulating substrate 1 to a drilling method or the like. In addition, a conductive layer 6 made of a metal material such as copper, aluminum, silver, or nickel is formed on the inside, the upper and lower surfaces, and the inner wall of the through hole 5 of the insulating substrate 1.

【００１８】前記絶縁基板１の内部、上下両面及び貫通
孔５の内壁に形成されている導電層６は後述する絶縁基
板１の上面に形成される多層配線部４の薄膜配線導体層
３と外部電気回路とを電気的に接続する、或いは多層配
線部４の薄膜配線導体層３同士を電気的に接続する、ま
たは絶縁基板１の上下両面に多層配線部４を配設した場
合には両面の多層配線部４の薄膜配線導体層同士を電気
的に接続する作用をなし、絶縁基板１の内部及び上下両
面に形成されている導電層６は絶縁基板１を形成する各
ガラスエポキシ樹脂基板やビスマレイミドトリアジン基
板の上下面に銅やアルミニウム、銀、ニッケル、鉄等の
金属材料から成る金属材料箔を被着させておき、これを
エッチング加工技術を用いて所定パターンに加工するこ
とによって形成され、また絶縁基板１の貫通孔５の内壁
に形成されている導電層６は貫通孔５の内壁に従来周知
のめっき法を採用することによって銅やニッケル、鉄等
の金属材料を被着させ、しかる後、これをエッチング加
工技術により所定パターンに加工することによって形成
される。The conductive layer 6 formed on the inside, the upper and lower surfaces, and the inner wall of the through hole 5 of the insulating substrate 1 is connected to the thin-film wiring conductor layer 3 of the multilayer wiring portion 4 formed on the upper surface of the insulating substrate 1 to be described later. When the thin film wiring conductor layers 3 of the multilayer wiring portion 4 are electrically connected to an electric circuit, or when the multilayer wiring portion 4 is disposed on both the upper and lower surfaces of the insulating substrate 1, both the thin film wiring conductor layers 3 The conductive layers 6 formed inside the insulating substrate 1 and on both upper and lower surfaces serve to electrically connect the thin film wiring conductor layers of the multilayer wiring portion 4 to each other. A metal material foil made of a metal material such as copper, aluminum, silver, nickel, or iron is applied to the upper and lower surfaces of the maleimide triazine substrate, and is formed by processing it into a predetermined pattern using an etching technique. In addition, the conductive layer 6 formed on the inner wall of the through hole 5 of the insulating substrate 1 is made to adhere a metal material such as copper, nickel, or iron to the inner wall of the through hole 5 by employing a conventionally known plating method. Thereafter, it is formed by processing this into a predetermined pattern by an etching processing technique.

【００１９】更に前記絶縁基板１はその内部で、且つ外
周部に、絶縁基板１の内部に形成されている導電層６を
取り囲むようにして枠状の金属層７が埋設されており、
該金属層７によって絶縁基板１の外力に対する機械的強
度が大幅に増大され、絶縁基板１の上面に後述する多層
配線部４の有機樹脂絶縁層２を形成する際、絶縁基板１
に有機樹脂絶縁層２の熱硬化時に発生する応力が作用し
たとしても絶縁基板１に大きな反りを発生することは殆
どない。Further, a frame-shaped metal layer 7 is buried inside the insulating substrate 1 and at the outer periphery thereof so as to surround the conductive layer 6 formed inside the insulating substrate 1.
The mechanical strength of the insulating substrate 1 against external force is greatly increased by the metal layer 7, and when the organic resin insulating layer 2 of the multilayer wiring portion 4 described later is formed on the upper surface of the insulating substrate 1, the insulating substrate 1
Even when the stress generated during the thermal curing of the organic resin insulating layer 2 acts on the insulating substrate 1, the insulating substrate 1 hardly generates a large warp.

【００２０】前記金属層７は例えば、導電層６と同様の
金属材料、具体的には銅やアルミニウム、銀、ニッケ
ル、鉄等の金属材料から成り、絶縁基板１の内部及び上
下面に導電層６を形成する際に、導電層６とともに該導
電層６を取り囲むようにして絶縁基板１の内部で、かつ
外周部に埋設される。The metal layer 7 is made of, for example, the same metal material as the conductive layer 6, specifically, a metal material such as copper, aluminum, silver, nickel, or iron. When forming the conductive layer 6, the conductive layer 6 is buried inside the insulating substrate 1 and in the outer peripheral portion so as to surround the conductive layer 6.

【００２１】前記金属層７は導電層６を取り囲むように
して絶縁基板１の外周部に形成されているため金属層７
が導電層６の形成に悪影響を与えることはなく、これに
よって絶縁基板１の内部に所定パターンの導電層６を形
成しつつ金属層７を形成することが可能となる。The metal layer 7 is formed on the outer peripheral portion of the insulating substrate 1 so as to surround the conductive layer 6.
Does not adversely affect the formation of the conductive layer 6, thereby making it possible to form the metal layer 7 while forming the conductive layer 6 in a predetermined pattern inside the insulating substrate 1.

【００２２】また前記金属層７は反りの大きさが最も大
きくなる絶縁基板１の外周部に枠状に形成されているた
め絶縁基板１の反り発生を効率よく防止することができ
るとともに絶縁基板１のいかなる方向の反りに対しても
その発生を有効に防止することができる。Further, since the metal layer 7 is formed in a frame shape on the outer peripheral portion of the insulating substrate 1 where the size of the warp is the largest, the occurrence of the warp of the insulating substrate 1 can be efficiently prevented and the insulating substrate 1 can be prevented. Can be effectively prevented from warping in any direction.

【００２３】なお、前記内部、上下両面及び貫通孔５の
内壁に導電層６が形成されている絶縁基板１は貫通孔５
の内部にエポキシ樹脂等からなる有機樹脂充填体８が充
填されており、該有機樹脂充填体８によって貫通孔５が
完全に埋められ、同時に有機樹脂充填体８の両端面が絶
縁基板１の上下両面に形成した導電層６の面と同一平面
となっている。The insulating substrate 1 in which the conductive layer 6 is formed on the inside, the upper and lower surfaces, and the inner wall of the through hole 5
Is filled with an organic resin filler 8 made of epoxy resin or the like, and the through hole 5 is completely filled with the organic resin filler 8. It is flush with the surface of the conductive layer 6 formed on both surfaces.

【００２４】前記有機樹脂充填体８は絶縁基板１の上面
及び／又は下面に後述する有機樹脂絶縁層２と薄膜配線
導体層３とから成る多層配線部４を形成する際、多層配
線部４の有機樹脂絶縁層２と薄膜配線導体層３の平坦化
を維持する作用をなし、絶縁基板１の貫通孔５内にエポ
キシ樹脂等の前駆体を充填し、しかる後、これに８０〜
２００℃の温度を０．５〜３時間印加し、完全に熱硬化
させることによって絶縁基板１の貫通孔５内に充填され
る。The organic resin filler 8 is used to form a multilayer wiring portion 4 comprising an organic resin insulating layer 2 and a thin film wiring conductor layer 3 on the upper surface and / or lower surface of the insulating substrate 1 when the multilayer wiring portion 4 is formed. It serves to maintain the flatness of the organic resin insulating layer 2 and the thin-film wiring conductor layer 3 and fills the through-hole 5 of the insulating substrate 1 with a precursor such as an epoxy resin.
A temperature of 200 ° C. is applied for 0.5 to 3 hours, and the thermosetting is completely performed to fill the through holes 5 of the insulating substrate 1.

【００２５】更に前記絶縁基板１はその上面に有機樹脂
絶縁層２と薄膜配線導体層３とが交互に多層に積層され
た多層配線部４が形成されており、且つ薄膜配線導体層
３の一部は導電層６と電気的に接続されている。The insulating substrate 1 further has a multilayer wiring portion 4 on the upper surface of which an organic resin insulating layer 2 and a thin film wiring conductor layer 3 are alternately laminated in multiple layers. The part is electrically connected to the conductive layer 6.

【００２６】前記多層配線部４を構成する有機樹脂絶縁
層２は上下に位置する薄膜配線導体層３の電気的絶縁を
図る作用をなし、薄膜配線導体層３は電気信号を伝達す
るための伝達路として作用する。The organic resin insulating layer 2 constituting the multi-layer wiring section 4 functions to electrically insulate the thin film wiring conductor layer 3 located above and below, and the thin film wiring conductor layer 3 is used for transmitting electric signals. Acts as a road.

【００２７】前記多層配線部４の有機樹脂絶縁層２はエ
ポキシ樹脂、ビスマレイミドトリアジド樹脂、ポリフェ
ニレンエーテル樹脂、ふっ素樹脂等の有機樹脂から成
り、例えば、エポキシ樹脂からなる場合、ビスフェノー
ルＡ型エポキシ樹脂、ノボラック型エポキシ樹脂、グリ
シジルエステル型エポキシ樹脂等にアミン系硬化剤、イ
ミダゾール糸硬化剤、酸無水物系硬化剤等の硬化剤を添
加混合してペースト状のエポキシ樹脂前駆体を得るとと
もに該エポキシ樹脂前駆体を絶縁基板１の上部にスピン
コート法により被着させ、しかる後、これを約８０℃〜
２００℃の熱で０．５乃至３時間熱処理し、熱硬化させ
ることによって形成される。The organic resin insulating layer 2 of the multilayer wiring section 4 is made of an organic resin such as an epoxy resin, a bismaleimide triazide resin, a polyphenylene ether resin, and a fluororesin. , A novolak type epoxy resin, a glycidyl ester type epoxy resin, and the like, and a curing agent such as an amine curing agent, an imidazole thread curing agent, an acid anhydride curing agent, etc., are added and mixed to obtain a paste-like epoxy resin precursor and the epoxy resin. A resin precursor is applied to the upper portion of the insulating substrate 1 by a spin coating method.
It is formed by heat-treating with heat of 200 ° C. for 0.5 to 3 hours and heat curing.

【００２８】また前記有機樹脂絶縁層２はその各々の所
定位置に最小径が有機樹脂絶縁層２の厚みに対して約
１．５倍程度のスルーホール９が形成されており、該ス
ルーホール９は後述する有機樹脂絶縁層２を挟んで上下
に位置する薄膜配線導体層３の各々を電気的に接続する
スルーホール導体１０を形成するための形成孔として作
用する。The organic resin insulating layer 2 has a through hole 9 having a minimum diameter of about 1.5 times the thickness of the organic resin insulating layer 2 at each predetermined position. Serves as a forming hole for forming a through-hole conductor 10 that electrically connects each of the thin film wiring conductor layers 3 located above and below the organic resin insulating layer 2 described later.

【００２９】前記有機樹脂絶縁層２に設けるスルーホー
ル９は例えば、フォトリソグラフイー技術、具体的には
有機樹脂絶縁層２上にレジスト材を塗布するとともにこ
れに露光、現像を施すことによって所定位置に所定形状
の窓部を形成し、次に前記レジスト材の窓部にエッチン
グ液を配し、レジスト材の窓部に位置する有機樹脂絶縁
層２を除去して、有機樹脂絶縁層２に穴（スルーホー
ル）を形成し、最後に前記レジスト材を有機樹脂絶縁層
２上より剥離させ除去することによって行われる。The through holes 9 provided in the organic resin insulating layer 2 are formed at predetermined positions by, for example, photolithography, specifically, applying a resist material onto the organic resin insulating layer 2 and exposing and developing the resist material. Then, a window having a predetermined shape is formed, and then an etchant is disposed on the window of the resist material, the organic resin insulating layer 2 located on the window of the resist material is removed, and a hole is formed in the organic resin insulating layer 2. (Through holes), and finally, the resist material is peeled off from the organic resin insulating layer 2 and removed.

【００３０】更に前記各有機樹脂絶縁層２の上面には所
定パターンの薄膜配線導体層３が、また各有機樹脂絶縁
層２に設けたスルーホール９の内壁にはスルーホール導
体１０が各々配設されており、スルーホール導体１０に
よって間に有機樹脂絶縁層２を挟んで上下に位置する各
薄膜配線導体層３の各々が電気的に接続されるようにな
っている。Further, a thin-film wiring conductor layer 3 having a predetermined pattern is provided on the upper surface of each organic resin insulating layer 2, and a through-hole conductor 10 is provided on the inner wall of a through hole 9 provided in each organic resin insulating layer 2. Each of the thin-film wiring conductor layers 3 positioned above and below the organic resin insulating layer 2 with the through-hole conductor 10 therebetween is electrically connected.

【００３１】前記各有機樹脂絶縁層２の上面及びスルー
ホール９内に配設される薄膜配線導体層３及びスルーホ
ール導体１０は銅、ニッケル、金、アルミニウム等の金
属材料を無電解めっき法や蒸着法、スパッタリング法等
の薄膜形成技術及びエッチング加工技術を採用すること
によって形成され、例えば銅で形成されている場合に
は、有機樹脂絶縁層２の上面及びスルーホール９の内壁
面に硫酸銅０．０６モル／リットル、ホルマリン０．３
モル／リットル、水酸化ナトリウム０．３５モル／リッ
トル、エチレンジアミン四酢酸０．３５モル／リットル
からなる無電解銅めっき浴を用いて厚さ１μｍ乃至４０
μｍの銅層を被着させ、しかる後、前記銅層をエッチン
グ加工技術により所定パターンに加工することによって
各有機樹脂絶縁層２間及び各有機樹脂絶縁層２のスルー
ホール９内壁に配設される。この場合、薄膜配線導体層
３は薄膜形成技術により形成されることから配線の微細
化が可能であり、これによって薄膜配線導体層３を極め
て高密度に形成することが可能となる。The thin-film wiring conductor layer 3 and the through-hole conductor 10 provided on the upper surface of each of the organic resin insulating layers 2 and in the through-holes 9 are made of a metal material such as copper, nickel, gold, or aluminum by electroless plating. It is formed by employing a thin film forming technique such as a vapor deposition method and a sputtering method and an etching technique. For example, in the case of being formed of copper, copper sulfate is formed on the upper surface of the organic resin insulating layer 2 and the inner wall surface of the through hole 9. 0.06 mol / l, formalin 0.3
Mol / l, sodium hydroxide 0.35 mol / l, and ethylenediaminetetraacetic acid 0.35 mol / l using an electroless copper plating bath having a thickness of 1 μm to 40 μm.
A copper layer having a thickness of μm is deposited, and thereafter, the copper layer is processed into a predetermined pattern by an etching processing technique to be disposed between the organic resin insulating layers 2 and on the inner wall of the through hole 9 of each organic resin insulating layer 2. You. In this case, since the thin-film wiring conductor layer 3 is formed by a thin-film forming technique, the wiring can be miniaturized, thereby making it possible to form the thin-film wiring conductor layer 3 at an extremely high density.

【００３２】なお、前記有機樹脂絶縁層２と薄膜配線導
体層３とを交互に多層に積層して形成される多層配線部
４は各有機樹脂絶縁層２の上面を中心線平均粗さ（Ｒ
ａ）で０．０５μｍ≦Ｒａ≦５μｍの粗面としておく
と、有機樹脂絶縁層２と薄膜配線導体層３との接合及び
上下に位置する有機樹脂絶縁層２同士の接合を強固とな
すことができる。従って、前記多層配線部４の各有機樹
脂絶縁層２はその上面をエッチング加工技術等を採用す
ることによって粗し、中心線平均粗さ（Ｒａ）で０．０
５μｍ≦Ｒａ≦５μｍの粗面としておくことが好まし
い。The multilayer wiring portion 4 formed by alternately laminating the organic resin insulating layers 2 and the thin film wiring conductor layers 3 in a multilayer structure has a center line average roughness (R
If a rough surface of 0.05 μm ≦ Ra ≦ 5 μm is set in a), the bonding between the organic resin insulating layer 2 and the thin-film wiring conductor layer 3 and the bonding between the organic resin insulating layers 2 located above and below can be made strong. it can. Accordingly, the upper surface of each organic resin insulating layer 2 of the multilayer wiring section 4 is roughened by employing an etching technique or the like, and has a center line average roughness (Ra) of 0.0%.
It is preferable to provide a rough surface of 5 μm ≦ Ra ≦ 5 μm.

【００３３】また前記有機樹脂絶縁層２はその表面の
２．５ｍｍの長さにおける凹凸の高さ（Ｐｃ）のカウン
ト値を、１μｍ≦Ｐｃ≦１０μｍが５００個以上、０．
１μｍ≦Ｐｃ≦１μｍが２５００個以上、０．０１μｍ
≦Ｐｃ≦０．１μｍが１２５００以上としておくと有機
樹脂絶縁層２と薄膜配線導体層３との接合及び上下に位
置する有機樹脂絶縁層２同士の接合がより強固となる。
従って、前記有機樹脂絶縁層２はその表面の２．５ｍｍ
の長さにおける凹凸の高さ（Ｐｃ）のカウント値を、１
μｍ≦Ｐｃ≦１０μｍが５００個以上、０．１μｍ≦Ｐ
ｃ≦１μｍが２５００個以上、０．０１μｍ≦Ｐｃ≦
０．１μｍが１２５００以上としておくことが好まし
い。The count value of the height of unevenness (Pc) of the organic resin insulating layer 2 at a length of 2.5 mm on the surface is 500 or more for 1 μm ≦ Pc ≦ 10 μm.
2500 μm of 1 μm ≦ Pc ≦ 1 μm, 0.01 μm
When ≦ Pc ≦ 0.1 μm is set to 12500 or more, the bonding between the organic resin insulating layer 2 and the thin-film wiring conductor layer 3 and the bonding between the organic resin insulating layers 2 located above and below become stronger.
Therefore, the organic resin insulating layer 2 has a surface of 2.5 mm
The count value of the height of irregularities (Pc) in the length of
500 μm ≦ Pc ≦ 10 μm or more, 0.1 μm ≦ P
2500 or more when c ≦ 1 μm, 0.01 μm ≦ Pc ≦
It is preferable that 0.1 μm is 12500 or more.

【００３４】前記有機樹脂絶縁層２上面の中心線平均粗
さ（Ｒａ）及び２．５ｍｍの長さにおける凹凸の高さ
（Ｐｃ）のカウント値は、有機樹脂絶縁層２の表面を原
子間力顕微鏡（Digital Instruments Inc.製のDimensio
n 3000-Nano Scope III)で５０μｍ角の対角（７０μ
ｍ）に走査させてその表面状態を検査測定し、その測定
結果より各々の数値を算出した。The count value of the center line average roughness (Ra) of the upper surface of the organic resin insulating layer 2 and the height of the unevenness (Pc) at a length of 2.5 mm are obtained by measuring the surface of the organic resin insulating layer 2 with an atomic force. Microscope (Dimensio manufactured by Digital Instruments Inc.
n 3000-Nano Scope III)
m), the surface condition was inspected and measured, and each numerical value was calculated from the measurement result.

【００３５】また前記中心線平均粗さ（Ｒａ）が０．０
５μｍ≦Ｒａ≦５μｍ、２．５ｍｍの長さにおける凹凸
の高さ（Ｐｃ）のカウント値を、１μｍ≦Ｐｃ≦１０μ
ｍが５００個以上、０．１μｍ≦Ｐｃ≦１μｍが２５０
０個以上、０．０１μｍ≦Ｐｃ≦０．１μｍが１２５０
０以上の有機樹脂絶縁層２は、該有機樹脂絶縁層２の上
面にＣＨＦ3 、ＣＦ4 、Ａｒ等のガスを吹きつけリアク
ティブイオンエッチング処理することによって表面が所
定の粗さに粗らされる。The center line average roughness (Ra) is 0.0
5 μm ≦ Ra ≦ 5 μm, the count value of the height (Pc) of the unevenness at a length of 2.5 mm is 1 μm ≦ Pc ≦ 10 μm
m is 500 or more, and 0.1 μm ≦ Pc ≦ 1 μm is 250
0 or more, 0.01 μm ≦ Pc ≦ 0.1 μm is 1250
The surface of the organic resin insulating layer 2 having zero or more is roughened to a predetermined roughness by performing a reactive ion etching process by blowing a gas such as CHF 3 , CF 4 , or Ar onto the upper surface of the organic resin insulating layer 2. You.

【００３６】更に前記有機樹脂絶縁層２はその各々の厚
みが１００μｍを超えると有機樹脂絶縁層２にフォトリ
ソグラフイー技術を採用することによってスルーホール
９を形成する際、エッチングの加工時間が長くなってス
ルーホール９を所望する鮮明な形状に形成するのが困難
となり、また５μｍ未満となると有機樹脂絶縁層２の上
面に上下に位置する有機樹脂絶縁層２の接合強度を上げ
るための粗面加工を施す際、有機樹脂絶縁層２に不要な
穴が形成され上下に位置する薄膜配線導体層３に不要な
電気的短絡を招来してしまう危険性がある。従って、前
記有機樹脂絶縁層２はその各々の厚みを５μｍ乃至１０
０μｍの範囲としておくことが好ましい。Further, when the thickness of each of the organic resin insulating layers 2 exceeds 100 μm, the etching processing time becomes longer when the through holes 9 are formed by employing photolithography technology in the organic resin insulating layers 2. It is difficult to form the through hole 9 into a desired sharp shape, and if it is less than 5 μm, rough surface processing for increasing the bonding strength of the organic resin insulating layer 2 located above and below the upper surface of the organic resin insulating layer 2. When applying, there is a risk that an unnecessary hole is formed in the organic resin insulating layer 2 and an unnecessary electrical short circuit occurs in the thin film wiring conductor layer 3 located above and below. Accordingly, the organic resin insulating layer 2 has a thickness of 5 μm to 10 μm.
It is preferable to set the range to 0 μm.

【００３７】また更に前記多層配線部４の各薄膜配線導
体層３はその厚みが３μｍ未満であると薄膜配線導体層
３の電気抵抗値が大きなものとなって各薄膜配線導体層
３に所定の電気信号を伝達させることが困難となり、ま
た４０μｍを超えると薄膜配線導体層３を有機樹脂絶縁
層２に被着させる際に薄膜配線導体層３の内部に大きな
応力が内在し、該大きな内在応力によって薄膜配線導体
層３が有機樹脂絶縁層２から剥離し易いものとなる。従
って、前記多層配線部４の各薄膜配線導体層３の厚みは
１μｍ乃至４０μｍの範囲としておくことが好ましい。Further, when the thickness of each thin-film wiring conductor layer 3 of the multilayer wiring portion 4 is less than 3 μm, the electric resistance of the thin-film wiring conductor layer 3 becomes large, so that each thin-film wiring conductor layer 3 has a predetermined thickness. It is difficult to transmit an electric signal. If the thickness exceeds 40 μm, a large stress is present inside the thin-film wiring conductor layer 3 when the thin-film wiring conductor layer 3 is applied to the organic resin insulating layer 2. Thereby, the thin film wiring conductor layer 3 is easily peeled off from the organic resin insulating layer 2. Therefore, it is preferable that the thickness of each thin-film wiring conductor layer 3 of the multilayer wiring portion 4 be in the range of 1 μm to 40 μm.

【００３８】前記有機樹脂絶縁層２と薄膜配線導体層３
とを交互に多層に配設して形成される多層配線部４は更
に、最上層の有機樹脂絶縁層２の上面に薄膜配線導体層
３と電気的に接続しているボンディングパッド１１が形
成されており、該ボンディングパッド１１は半導体素子
や容量素子、抵抗器等の電子部品Ａの電極を薄膜配線導
体層３に電気的に接続する作用をなす。The organic resin insulating layer 2 and the thin-film wiring conductor layer 3
Are formed alternately in multiple layers, and a bonding pad 11 that is electrically connected to the thin film wiring conductor layer 3 is further formed on the upper surface of the uppermost organic resin insulating layer 2. The bonding pad 11 functions to electrically connect the electrodes of the electronic component A such as a semiconductor element, a capacitance element, and a resistor to the thin film wiring conductor layer 3.

【００３９】前記ボンディングパッド１１は絶縁基板１
の内部で、かつ外周部に埋設した金属層７によって絶縁
基板１に反りが発生していないことからその全てが略同
一の平面に存在することとなり、その結果、ボンディン
グパッド１１に半導体素子や容量素子、抵抗器等の電子
部品Ａの電極を確実、強固に電気的接続することが可能
となる。The bonding pads 11 correspond to the insulating substrate 1
Since the insulating substrate 1 is not warped by the metal layer 7 buried inside and at the outer peripheral portion thereof, all of them are present on substantially the same plane. Electrodes of the electronic component A such as elements and resistors can be reliably and firmly electrically connected.

【００４０】前記ボンディングパッド１１は例えば、直
径２００〜５００μｍの円形状をなしており、該ボンデ
ィングパッド１１に半導体素子や容量素子等の電子部品
Ａの電極を熱圧着等により接続させれば、半導体素子や
容量素子等の電子部品Ａの電極は薄膜配線導体層３に電
気的に接続されることとなる。The bonding pad 11 has, for example, a circular shape with a diameter of 200 to 500 μm. If electrodes of an electronic component A such as a semiconductor element and a capacitor element are connected to the bonding pad 11 by thermocompression or the like, a semiconductor is formed. The electrodes of the electronic component A such as the element and the capacitor are electrically connected to the thin-film wiring conductor layer 3.

【００４１】なお、前記ボンディングパッド１１は薄膜
配線導体層３と同じ金属材料、具体的には銅、ニッケ
ル、金、アルミニウム等の金属材料から成り、最上層の
有機樹脂絶縁層２上に薄膜配線導体層３を形成する際に
同時に前記薄膜配線導体層３と電気的接続をもって形成
される。The bonding pad 11 is made of the same metal material as the thin film wiring conductor layer 3, specifically, a metal material such as copper, nickel, gold, aluminum or the like. When the conductor layer 3 is formed, it is formed at the same time as the thin-film wiring conductor layer 3 with electrical connection.

【００４２】かくして上述の多層配線基板によれば、最
上層の有機樹脂絶縁層２上面に設けたボンディングパッ
ド１１に半導体素子や容量素子等の電子部品Ａの電極を
熱圧着等により接続させ、電子部品Ａの電極をボンディ
ングパッド１１を介して薄膜配線導体層３に電気的に接
続させることによって半導体装置や混成集積回路装置と
なり、薄膜配線導体層３を導電層６を介して外部電気回
路に接続すれば前記電子部品Ａが外部電気回路に接続さ
れることとなる。Thus, according to the above-described multilayer wiring board, the electrodes of the electronic component A such as a semiconductor element and a capacitor element are connected to the bonding pad 11 provided on the uppermost organic resin insulating layer 2 by thermocompression or the like. By electrically connecting the electrodes of the component A to the thin-film wiring conductor layer 3 via the bonding pads 11, a semiconductor device or a hybrid integrated circuit device is obtained. The thin-film wiring conductor layer 3 is connected to an external electric circuit via the conductive layer 6. Then, the electronic component A is connected to an external electric circuit.

【００４３】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば、上述の実施例におい
ては絶縁基板１の上面のみに有機樹脂絶縁層２と薄膜配
線導体層３とから成る多層配線部４を設けたが、多層配
線部４を絶縁基板１の下面側のみに設けても、上下の両
面に設けてもよい。It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. The multilayer wiring portion 4 composed of the organic resin insulating layer 2 and the thin film wiring conductor layer 3 is provided only on the upper surface of the insulating substrate 1. However, the multilayer wiring portion 4 may be provided only on the lower surface side of the insulating substrate 1 or provided on both upper and lower surfaces. Is also good.

【００４４】[0044]

【発明の効果】本発明の多層配線基板によれば、絶縁基
板上に薄膜形成技術によって配線の一部を形成したこと
から配線の微細化が可能となり、従来に比べて配線を極
めて高密度に形成することが可能となる。According to the multilayer wiring board of the present invention, since a part of the wiring is formed on the insulating substrate by the thin film forming technique, the wiring can be miniaturized. It can be formed.

【００４５】また本発明の多層配線基板によれば、内部
及び表面に導電層が形成されている絶縁基板の内部で、
かつ外周部に、絶縁基板内部に形成されている導電層を
取り囲むようにして枠状の金属層を埋設させたことから
絶縁基板の反りに対する強度が増大し、絶縁基板上に有
機樹脂絶縁層を形成する際、絶縁基板に有機樹脂絶縁層
の熱硬化時に発生する応力が作用したとしても絶縁基板
に大きな反りが発生することは殆どなく、その結果、ボ
ンディングパッドの形成位置が同一の平面となり、ボン
ディングパッドに半導体素子等の能動部品や容量素子、
抵抗器等の受動部品の電極を確実、且つ強固に電気的接
続することが可能となる。According to the multilayer wiring board of the present invention, the inside of the insulating substrate having the conductive layer formed inside and on the surface thereof is
In addition, since the frame-shaped metal layer is buried in the outer peripheral portion so as to surround the conductive layer formed inside the insulating substrate, the strength against warpage of the insulating substrate increases, and the organic resin insulating layer is formed on the insulating substrate. At the time of formation, even if stress generated at the time of thermal curing of the organic resin insulating layer acts on the insulating substrate, there is almost no occurrence of large warpage in the insulating substrate, and as a result, the formation positions of the bonding pads are on the same plane, Active components such as semiconductor elements and capacitive elements on bonding pads,
Electrodes of passive components such as resistors can be reliably and firmly electrically connected.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の多層配線基板の一実施例を示す断面図
である。FIG. 1 is a sectional view showing one embodiment of a multilayer wiring board of the present invention.

【符号の説明】[Explanation of symbols]

１・・・絶縁基板 ２・・・有機樹脂絶縁層 ３・・・薄膜配線導体 ４・・・多層配線部 ５・・・貫通孔 ６・・・導電層 ７・・・金属層 ９・・・スルーホール １０・・スルーホール導体 １１・・ボンディングパッド Ａ・・・電子部品 DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Organic resin insulating layer 3 ... Thin film wiring conductor 4 ... Multilayer wiring part 5 ... Through-hole 6 ... Conductive layer 7 ... Metal layer 9 ... Through-hole 10, through-hole conductor 11, bonding pad A: electronic component

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】内部及び表面に導電層が形成されている絶
縁基板の少なくとも一主面上に、有機樹脂絶縁層と薄膜
配線導体層とを交互に積層するとともに上下に位置する
薄膜配線導体層を有機樹脂絶縁層に設けたスルーホール
導体を介して電気的に接続して成り、最上層の有機樹脂
絶縁層上面に、前記薄膜配線導体層と電気的に接続し、
外部の電子部品が接続されるボンディングパッドを設け
て成る多層配線基板であって、前記絶縁基板はその内部
で、かつ外周部に、絶縁基板内部に形成されている導電
層を取り囲むように枠状の金属層が埋設されていること
を特徴とする多層配線基板。An organic resin insulating layer and a thin-film wiring conductor layer are alternately laminated on at least one principal surface of an insulating substrate having a conductive layer formed therein and on a surface thereof, and the thin-film wiring conductor layers located above and below are alternately stacked. Is electrically connected via a through-hole conductor provided in the organic resin insulating layer, on the upper surface of the uppermost organic resin insulating layer, electrically connected to the thin film wiring conductor layer,
A multilayer wiring board provided with bonding pads to which external electronic components are connected, wherein the insulating substrate has a frame shape inside and at an outer periphery thereof so as to surround a conductive layer formed inside the insulating substrate. A multilayer wiring board, wherein the metal layer is embedded.
JP9132153A 1997-05-22 1997-05-22 Multilayered wiring board Pending JPH10322030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9132153A JPH10322030A (en) 1997-05-22 1997-05-22 Multilayered wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9132153A JPH10322030A (en) 1997-05-22 1997-05-22 Multilayered wiring board

Publications (1)

Publication Number Publication Date
JPH10322030A true JPH10322030A (en) 1998-12-04

Family

ID=15074607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9132153A Pending JPH10322030A (en) 1997-05-22 1997-05-22 Multilayered wiring board

Country Status (1)

Country Link
JP (1) JPH10322030A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002319762A (en) * 2001-04-20 2002-10-31 Toppan Printing Co Ltd Multilayer wiring board
CN108055758A (en) * 2017-12-05 2018-05-18 广州兴森快捷电路科技有限公司 The production method of blind buried via hole circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002319762A (en) * 2001-04-20 2002-10-31 Toppan Printing Co Ltd Multilayer wiring board
CN108055758A (en) * 2017-12-05 2018-05-18 广州兴森快捷电路科技有限公司 The production method of blind buried via hole circuit board
CN108055758B (en) * 2017-12-05 2020-04-10 广州兴森快捷电路科技有限公司 Manufacturing method of blind buried hole circuit board

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