JPH09512371A - データ通信バスを有する回路 - Google Patents
データ通信バスを有する回路Info
- Publication number
- JPH09512371A JPH09512371A JP8518511A JP51851196A JPH09512371A JP H09512371 A JPH09512371 A JP H09512371A JP 8518511 A JP8518511 A JP 8518511A JP 51851196 A JP51851196 A JP 51851196A JP H09512371 A JPH09512371 A JP H09512371A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- circuit
- level
- bus line
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004891 communication Methods 0.000 title claims abstract description 29
- 230000008878 coupling Effects 0.000 claims description 11
- 238000010168 coupling process Methods 0.000 claims description 11
- 238000005859 coupling reaction Methods 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 6
- 101150111792 sda1 gene Proteins 0.000 description 4
- 101150075681 SCL1 gene Proteins 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005265 energy consumption Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000009849 deactivation Effects 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Dc Digital Transmission (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
- Bus Control (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.それぞれ優勢または劣性モードで選択的にバスを駆動してデータを送信する ために配置された複数の補助回路が結合された通信バスを有する回路であって、 前記バスが、前記補助回路の何れかが優勢モードで前記バスを駆動する場合に優 勢状態に到り、そして全ての補助回路が劣性状態で前記バスを駆動する場合に劣 性状態に到るために配置され、前記補助回路が、前記バスの状態を検出してデー タを受信するために配置され、前記バスが、中継インタフェースを介して相互結 合された第1及び第2バスラインを有し、前記第1及び第2バスラインの各々が 、自己に結合された少なくとも一つの補助回路を有し、前記優勢及び劣性モード の各々が、前記第1及び第2バスラインの電位である優勢及び劣性レベルに対応 し、前記中継インタフェースが、前記第1及び第2バスラインの電位に論理的に 対応するレベルを設定するために配置されたデータ通信バスを有する回路におい て、 優勢モードの駆動が存在しない状況において、かつ互いに独立して個別の劣性 レベルを示す第1及び第2バスの電位を設けるために配置された手段を有し、 前記中継装置が、前記第1及び/もしくは第2バスラインの電位が優勢レベル と対応するバスラインの基準レベルとの間に位置するときに前記第1及び第2バ スラインの間の導通結合をもたらすため、そして前記第1及び第2バスラインの 電位が対応する前記バスラインの前記基準レベルと当該バスライン独自の劣性レ ベルとの間に位置するときに結合の遮断をもたらすために配置されたことを特徴 とする通信バスを有する回路。 2.請求項1に記載の回路において、 動作中、前記第1バスラインの劣性レベルと優勢レベルとの差である第1の差 が、前記第2バスラインの劣性レベルと優勢レベルとの差である第2の差よりも 小さくなるように設定されることを特徴とする通信バスを有する回路。 3.請求項1または2に記載の回路において、 前記中継インタフェースが、主電流チャネルと制御電極を有するトランジスタ を有し、 前記主電流チャネルを介して延在する前記第1及び第2バスラインと前記制御 電 極との間の結合が、所定のレベルからトランジスタの閾電圧を引いた電位に対応 する所定のレベルの電位に結合されることを特徴とする通信バスを有する回路。 4.請求項3に記載の回路において、 前記トランジスタがNチャネルの通常オフ状態のIGFETもしくはMOSFETである ことを特徴とする通信バスを有する回路。 5.請求項3に記載の回路において、 前記トランジスタがバイポーラトランジスタであることを特徴とする通信バス を有する回路。 6.請求項4または5に記載の回路において、 前記トランジスタの制御電極が、前記第2バスラインの劣性レベルの電位を受 信することを特徴とする通信バスを有する回路。 7.請求項1乃至6の何れか一項に記載の回路において、 前記補助回路もしくは前記第2バスラインに結合された補助回路へのエネルギ 供給を遮断する状態と、 前記第2バスラインの電位の劣性レベルを実質的な優勢レベルに下げる状態と 、 前記第1と第2バスラインとの間の結合を継続的に絶縁するために、前記基準 レベルを少なくとも前記優勢レベルに低減する状態とを得るためのスイッチ手段 を有することを特徴とする通信バスを有する回路。 8.請求項7に記載の回路において、 前記第1バスラインに結合された補助回路が制御のために前記スイッチ手段に 結合されることを特徴とする通信バスを有する回路。 9.請求項7または8に記載の回路において、 前記第2バスラインが連続的な結合と、第3バスラインと、機能的に当該結合 に類似した更なる結合を介して前記第1バスラインに結合され、優勢駆動が存在 しない劣性レベルに前記第3バスラインを駆動する手段を有することを特徴とす る通信バスを有する回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP94203510 | 1994-12-02 | ||
AT94203510.6 | 1994-12-02 | ||
PCT/IB1995/000975 WO1996017305A2 (en) | 1994-12-02 | 1995-11-08 | Circuit comprising a data communication bus |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09512371A true JPH09512371A (ja) | 1997-12-09 |
JP3698439B2 JP3698439B2 (ja) | 2005-09-21 |
Family
ID=8217424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51851196A Expired - Fee Related JP3698439B2 (ja) | 1994-12-02 | 1995-11-08 | データ通信バスを有する回路 |
Country Status (9)
Country | Link |
---|---|
US (1) | US5689196A (ja) |
EP (1) | EP0746820B1 (ja) |
JP (1) | JP3698439B2 (ja) |
KR (1) | KR100354939B1 (ja) |
CN (1) | CN1087453C (ja) |
DE (1) | DE69522928T2 (ja) |
HK (1) | HK1013695A1 (ja) |
TW (1) | TW311309B (ja) |
WO (1) | WO1996017305A2 (ja) |
Families Citing this family (89)
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DE19833693C2 (de) * | 1998-07-27 | 2002-11-07 | Wolf Gmbh Richard | Schnittstelle für I·2·C-Bus |
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US6622188B1 (en) * | 1998-09-30 | 2003-09-16 | International Business Machines Corporation | 12C bus expansion apparatus and method therefor |
US6753739B1 (en) | 1999-03-24 | 2004-06-22 | Cypress Semiconductor Corp. | Programmable oscillator scheme |
US6191660B1 (en) | 1999-03-24 | 2001-02-20 | Cypress Semiconductor Corp. | Programmable oscillator scheme |
US6946920B1 (en) | 2000-02-23 | 2005-09-20 | Cypress Semiconductor Corp. | Circuit for locking an oscillator to a data stream |
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US6297705B1 (en) | 2000-02-23 | 2001-10-02 | Cypress Semiconductor Corp. | Circuit for locking an oscillator to a data stream |
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US6724220B1 (en) | 2000-10-26 | 2004-04-20 | Cyress Semiconductor Corporation | Programmable microcontroller architecture (mixed analog/digital) |
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US7770113B1 (en) | 2001-11-19 | 2010-08-03 | Cypress Semiconductor Corporation | System and method for dynamically generating a configuration datasheet |
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US7809973B2 (en) * | 2005-11-16 | 2010-10-05 | Cypress Semiconductor Corporation | Spread spectrum clock for USB |
US8035455B1 (en) | 2005-12-21 | 2011-10-11 | Cypress Semiconductor Corporation | Oscillator amplitude control network |
US8085067B1 (en) | 2005-12-21 | 2011-12-27 | Cypress Semiconductor Corporation | Differential-to-single ended signal converter circuit and method |
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US8564252B2 (en) * | 2006-11-10 | 2013-10-22 | Cypress Semiconductor Corporation | Boost buffer aid for reference buffer |
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US8040266B2 (en) | 2007-04-17 | 2011-10-18 | Cypress Semiconductor Corporation | Programmable sigma-delta analog-to-digital converter |
US9564902B2 (en) | 2007-04-17 | 2017-02-07 | Cypress Semiconductor Corporation | Dynamically configurable and re-configurable data path |
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US8266575B1 (en) | 2007-04-25 | 2012-09-11 | Cypress Semiconductor Corporation | Systems and methods for dynamically reconfiguring a programmable system on a chip |
US9720805B1 (en) | 2007-04-25 | 2017-08-01 | Cypress Semiconductor Corporation | System and method for controlling a target device |
US8065653B1 (en) | 2007-04-25 | 2011-11-22 | Cypress Semiconductor Corporation | Configuration of programmable IC design elements |
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US9448964B2 (en) | 2009-05-04 | 2016-09-20 | Cypress Semiconductor Corporation | Autonomous control in a programmable system |
US8364870B2 (en) | 2010-09-30 | 2013-01-29 | Cypress Semiconductor Corporation | USB port connected to multiple USB compliant devices |
ITTO20110714A1 (it) * | 2011-08-01 | 2013-02-02 | Indesit Co Spa | Dispositivo di interfacciamento con una linea bus bidirezionale di tipo i2c |
US9667240B2 (en) | 2011-12-02 | 2017-05-30 | Cypress Semiconductor Corporation | Systems and methods for starting up analog circuits |
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IT201700043020A1 (it) | 2017-04-19 | 2018-10-19 | D E M S P A | Apparato elettronico con uscita a trasmissione digitale e seriale e dispositivo per misurare grandezze elettriche comprendente tale apparato elettronico |
KR102636496B1 (ko) * | 2018-09-14 | 2024-02-15 | 삼성전자주식회사 | 통신 장치 및 이를 포함하는 전자 장치 |
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-
1995
- 1995-11-08 JP JP51851196A patent/JP3698439B2/ja not_active Expired - Fee Related
- 1995-11-08 KR KR1019960704189A patent/KR100354939B1/ko not_active IP Right Cessation
- 1995-11-08 DE DE69522928T patent/DE69522928T2/de not_active Expired - Lifetime
- 1995-11-08 EP EP95934797A patent/EP0746820B1/en not_active Expired - Lifetime
- 1995-11-08 CN CN95192051A patent/CN1087453C/zh not_active Expired - Lifetime
- 1995-11-08 WO PCT/IB1995/000975 patent/WO1996017305A2/en active IP Right Grant
- 1995-12-01 US US08/565,774 patent/US5689196A/en not_active Expired - Lifetime
- 1995-12-27 TW TW084113945A patent/TW311309B/zh not_active IP Right Cessation
-
1998
- 1998-12-23 HK HK98114919A patent/HK1013695A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW311309B (ja) | 1997-07-21 |
DE69522928T2 (de) | 2002-04-11 |
DE69522928D1 (de) | 2001-10-31 |
WO1996017305A3 (en) | 1996-08-08 |
KR100354939B1 (ko) | 2003-02-05 |
EP0746820B1 (en) | 2001-09-26 |
EP0746820A1 (en) | 1996-12-11 |
US5689196A (en) | 1997-11-18 |
CN1144003A (zh) | 1997-02-26 |
CN1087453C (zh) | 2002-07-10 |
WO1996017305A2 (en) | 1996-06-06 |
KR970700880A (ko) | 1997-02-12 |
HK1013695A1 (en) | 1999-09-03 |
JP3698439B2 (ja) | 2005-09-21 |
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