JPH05198851A - Resistor for josephson integrated circuit and its manufacture - Google Patents
Resistor for josephson integrated circuit and its manufactureInfo
- Publication number
- JPH05198851A JPH05198851A JP4008812A JP881292A JPH05198851A JP H05198851 A JPH05198851 A JP H05198851A JP 4008812 A JP4008812 A JP 4008812A JP 881292 A JP881292 A JP 881292A JP H05198851 A JPH05198851 A JP H05198851A
- Authority
- JP
- Japan
- Prior art keywords
- film
- transition metal
- resistor
- superconductor
- nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は，ジョセフソン集積回路
用抵抗体の製造方法に関する。近年，ジョセフソン集積
回路は高速, 低消費電力, 及び, 高磁界感度を特徴とし
て, 将来の高速コンピュータ, 或いは, 生体磁気測定用
にその応用が注目されている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a resistor for Josephson integrated circuits. In recent years, Josephson integrated circuits are characterized by high speed, low power consumption, and high magnetic field sensitivity, and their applications have been attracting attention for future high-speed computers or biomagnetic measurements.
【０００２】この集積回路の構成要素としては, ジョセ
フソン接合, 抵抗体の二つがある。本発明はこのうちの
抵抗体の製造に係わるものである。There are two components of this integrated circuit, a Josephson junction and a resistor. The present invention relates to the production of the resistor.
【０００３】[0003]
【従来の技術】図３は従来例の説明図である。図におい
て，15はSiO2膜, 16はMo膜, 17は第１のレジスト膜，18
は第２のレジスト膜，19はSiO 膜, 20はNb膜である。2. Description of the Related Art FIG. 3 is an explanatory view of a conventional example. In the figure, 15 is a SiO 2 film, 16 is a Mo film, 17 is a first resist film, 18
Is a second resist film, 19 is a SiO 2 film, and 20 is a Nb film.
【０００４】従来, ジョセフソン集積回路用抵抗体とし
ては, モリブデン(Mo)の薄膜が使用されていた。従来の
Mo抵抗体の製造方法について, 図２により説明する。Conventionally, a thin film of molybdenum (Mo) has been used as a resistor for a Josephson integrated circuit. Traditional
A method of manufacturing the Mo resistor will be described with reference to FIG.
【０００５】図３（ａ）に示すように，シリコン(Si)基
板に形成された二酸化シリコン(SiO2)膜15上にMo膜16を
約 150Åの厚さに堆積する。Mo膜16の堆積はDCマグネト
ロンスパッタで真空度 1.3Pa, 印加電力１kw, 堆積速度
3,000Å/minで行う。As shown in FIG. 3A, a Mo film 16 is deposited on the silicon dioxide (SiO 2 ) film 15 formed on a silicon (Si) substrate to a thickness of about 150 Å. Mo film 16 was deposited by DC magnetron sputtering, vacuum degree 1.3Pa, applied power 1kw, deposition rate
Perform at 3,000Å / min.
【０００６】次に, Mo膜16上に第１のレジスト膜17を塗
布し，リソグラフィにより抵抗体パターンに成形する。
図３（ｂ）に示すように，第１のレジスト膜17をマスク
として, 反応性イオンエッチング（ＲＩＥ）装置を用い
て，異方性ドライエッチングによりMo膜16をパターニン
グする。エッチングは反応ガスとして三弗化シランと酸
素(CHF3+O2) の混合ガスを用い，真空度８Pa, 印加電力
100Ｗで行う。Next, a first resist film 17 is applied on the Mo film 16 and formed into a resistor pattern by lithography.
As shown in FIG. 3B, using the first resist film 17 as a mask, the Mo film 16 is patterned by anisotropic dry etching using a reactive ion etching (RIE) device. The etching uses a mixed gas of silane trifluoride and oxygen (CHF 3 + O 2 ) as a reaction gas, the degree of vacuum is 8 Pa, and the applied power is
Perform at 100W.
【０００７】図３（ｃ）に示すように，Mo膜16の抵抗体
パターンの超伝導体膜との接続部を覆って, 第２のレジ
スト膜をSiO2膜15上にパターニングする。図３（ｄ）に
示すように，パターニングされた第２のレジスト膜18,
及び表出したMo膜16上全面にSiO 膜19を蒸着で 2,500Å
の厚さに堆積する。As shown in FIG. 3C, a second resist film is patterned on the SiO 2 film 15 so as to cover the connecting portion of the resistor pattern of the Mo film 16 with the superconductor film. As shown in FIG. 3D, the patterned second resist film 18,
And the SiO 2 film 19 is vapor-deposited on the entire exposed Mo film 16 by 2,500Å
Deposited to a thickness of.
【０００８】その後第２のレジスト膜をリフトオフする
と, Mo膜16の超伝導膜との接続部を残して, SiO 膜19で
被覆されるここととなる。図３（ｅ）に示すように，真
空装置内でMo膜16の表面をアルゴン(Ar)でエッチングし
てMo膜16表面の酸化層を除去した後, 配線層として超伝
導体膜であるニオブ(Nb)膜20を全面に 3,000Åの厚さに
堆積する。堆積はDCマグネトロンスパッタにより, Ar圧
力 1.3Pa, 印加電圧 300Ｖ，印加電流 2.0Ａでこの時の
堆積速度は300Å/minである。Then, when the second resist film is lifted off, the Mo film 16 is covered with the SiO 2 film 19 while leaving the connection portion with the superconducting film. As shown in FIG. 3E, the surface of the Mo film 16 is etched with argon (Ar) in a vacuum apparatus to remove the oxide layer on the surface of the Mo film 16, and then niobium, which is a superconductor film, is used as a wiring layer. A (Nb) film 20 is deposited on the entire surface to a thickness of 3,000Å. The deposition was carried out by DC magnetron sputtering at an Ar pressure of 1.3 Pa, an applied voltage of 300 V, and an applied current of 2.0 A. At this time, the deposition rate was 300 Å / min.
【０００９】図３（ｆ）に示すように，図示しないレジ
スト膜をマスクとして, Nb膜20をリソグラフィによりパ
ターニングしてNb膜20の配線層を形成する。エッチング
はＲＩＥ装置を用いて行う。反応ガスとして四弗化メタ
ンと酸素(CF4+O2)の混合ガスを用い, 真空度８Pa, 印加
電力50Ｗで行う。As shown in FIG. 3F, the Nb film 20 is patterned by lithography using a resist film (not shown) as a mask to form a wiring layer of the Nb film 20. Etching is performed using an RIE device. A mixed gas of methane tetrafluoride and oxygen (CF 4 + O 2 ) is used as a reaction gas, the degree of vacuum is 8 Pa, and the applied power is 50 W.
【００１０】レジスト膜を除去して，従来方法のMo膜20
を用いたジョセフソン集積回路の抵抗体を完成する。After removing the resist film, the Mo film of the conventional method 20
To complete a resistor for a Josephson integrated circuit using.
【００１１】[0011]
【発明が解決しようとする課題】しかしながら, 従来方
法による抵抗体の形成方法では,第１に，超伝導体のNb
膜配線層のパターン形成時に, Mo膜抵抗体も同時にエッ
チングされてしまうため, 図３（ｄ）に示したように，
エッチング防止層として, SiO 膜をMo膜抵抗体のパター
ン形成後に被覆することが必要となる。However, in the method of forming the resistor by the conventional method, firstly, the Nb of the superconductor is
Since the Mo film resistor is also etched at the same time when the pattern of the film wiring layer is formed, as shown in FIG.
As an etching prevention layer, it is necessary to cover the SiO 2 film after patterning the Mo film resistor.
【００１２】SiO 膜はリフトオフにより不要部分をレジ
スト膜と同時にリフトオフするが,SiO 膜は下地より剥
離しやすい欠点があり, 更に, プロセス工程が一つ増え
ることとなる。Although the unnecessary portion of the SiO 2 film is lifted off at the same time as the resist film by lift-off, the SiO 2 film has a drawback that it is easily peeled off from the underlying layer, which further increases the number of process steps.
【００１３】第２に，熱処理により，超伝導層とMo抵抗
体との間での拡散によって, 抵抗体超伝導層との接触抵
抗の増加が起こる。上記のような問題点を解決すること
を目的として, 本発明が提供される。Secondly, the heat treatment causes an increase in contact resistance with the resistor superconducting layer due to diffusion between the superconducting layer and the Mo resistor. The present invention is provided for the purpose of solving the above problems.
【００１４】[0014]
【課題を解決するための手段】図１は本発明の原理説明
図である。図において，１は絶縁膜，２は遷移金属膜，
３は遷移金属窒化膜，４は第１のレジスト膜，５は超伝
導体膜，６は第２のレジスト膜である。FIG. 1 illustrates the principle of the present invention. In the figure, 1 is an insulating film, 2 is a transition metal film,
3 is a transition metal nitride film, 4 is a first resist film, 5 is a superconductor film, and 6 is a second resist film.
【００１５】上記の問題点を解決するために，本発明に
おいては，第１の問題点を解決するために，Mo抵抗体に
換えて, Nb超伝導体膜のエッチング時にエッチングスト
ッパーとなるジルコニウム(Zr)やハフニウム(Hf)のよう
な遷移金属膜を抵抗体として採用する。In order to solve the above problems, in the present invention, in order to solve the first problem, in place of the Mo resistor, zirconium (etching stopper that acts as an etching stopper when etching the Nb superconductor film) is used. A transition metal film such as Zr) or hafnium (Hf) is adopted as the resistor.
【００１６】更に，第２の問題点を解決するために，超
伝導体膜と遷移金属抵抗体との熱処理時の拡散を防止す
るために，バリアとして遷移金属窒化物を超伝導体膜と
遷移金属抵抗体との間に挟み込む。Further, in order to solve the second problem, in order to prevent the diffusion of the superconductor film and the transition metal resistor during the heat treatment, a transition metal nitride is used as a barrier with the superconductor film. It is sandwiched between metal resistors.
【００１７】即ち，本発明の目的は，図１（ｆ）に示す
ように，絶縁膜１上の抵抗体パターンが，超伝導体膜５
のパターン形成時にエッチングストッパとなる遷移金属
２からなり，該遷移金属２と該超伝導体膜５との接続部
において，該遷移金属２は該遷移金属窒化物３を介して
該超伝導体膜５と接続してなることにより，前記遷移金
属２はジルコニウム, 或いは，ハフニウムからなり，前
記遷移金属窒化物３は窒化ジルコニウ, 或いは, 窒化ハ
ウニウムからなることにより，また，図１（ａ）に示す
ように，絶縁膜１上に遷移金属２と遷移金属窒化物３を
順次, 積層する工程と，図１（ｂ）〜（ｃ）に示すよう
に，該遷移金属窒化物３と該遷移金属２を第１のレジス
ト膜４をマスクとして, 抵抗体パターンにエッチングす
る工程と,図１（ｄ）に示すように，該遷移金属窒化物
３と該遷移金属２を覆って超伝導体膜５を被覆する工程
と,図１（ｅ）に示すように，第２のレジスト膜６をマ
スクとして, 抵抗パターンの両端に当たる該遷移金属窒
化膜３の該遷移金属膜２と該超伝導体膜５の接続部を残
して, 該遷移金属窒化膜３をエッチングする工程とを含
むことにより達成される。That is, as shown in FIG. 1 (f), the object of the present invention is that the resistor pattern on the insulating film 1 is the superconductor film 5
Of the transition metal 2 serving as an etching stopper at the time of pattern formation, the transition metal 2 at the connection portion between the transition metal 2 and the superconductor film 5 via the transition metal nitride 3 The transition metal 2 is composed of zirconium or hafnium, and the transition metal nitride 3 is composed of zirconium nitride or haunium nitride by being connected to the structure 5, as shown in FIG. 1 (a). As shown in FIGS. 1B to 1C, the transition metal nitride 3 and the transition metal nitride 3 are sequentially stacked on the insulating film 1. Using the first resist film 4 as a mask to etch a resistor pattern, and as shown in FIG. 1D, the transition metal nitride 3 and the transition metal 2 are covered to form a superconductor film 5. The coating process is shown in Fig. 1 (e). Then, using the second resist film 6 as a mask, the transition metal nitride film 3 is removed by leaving the connecting portions of the transition metal film 2 of the transition metal nitride film 3 and the superconductor film 5 which are both ends of the resistance pattern. And a step of etching.
【００１８】[0018]
【作用】本発明では，Mo抵抗体に換えて, Nb超伝導体膜
のエッチング時にエッチングストッパーとなるZrやHfの
ような遷移金属膜を抵抗体として採用しているため，Nb
超伝導体膜の配線形成において, Zr抵抗体がエッチング
ガスで侵されることがない。また, バリアとしてZrN 膜
等のような遷移金属窒化物をNb超伝導体膜とZrのような
遷移金属抵抗体との間に挟み込んでいるため, 超伝導体
膜と遷移金属抵抗体との熱処理時の拡散が防止できる。In the present invention, instead of the Mo resistor, a transition metal film such as Zr or Hf that serves as an etching stopper when etching the Nb superconductor film is used as the resistor.
The Zr resistor is not attacked by the etching gas when forming the wiring of the superconductor film. Moreover, since a transition metal nitride such as a ZrN film is sandwiched between the Nb superconductor film and a transition metal resistor such as Zr as a barrier, heat treatment of the superconductor film and the transition metal resistor is performed. The diffusion of time can be prevented.
【００１９】尚, 図１（ｅ）で, 縮尺の関係により, 超
伝導体膜と遷移金属抵抗体とが絶縁膜上で直接に接触し
ているように見えるが，遷移金属抵抗体は 0.1μｍと非
常に薄く, バリアとなる遷移金属窒化膜の面積に比して
微小のため, 接触抵抗は問題にならない。It should be noted that, in FIG. 1 (e), the superconducting film and the transition metal resistor appear to be in direct contact with each other on the insulating film due to the scale, but the transition metal resistor is 0.1 μm. The contact resistance is not a problem because it is extremely thin and is minute compared to the area of the transition metal nitride film that serves as a barrier.
【００２０】[0020]
【実施例】図２は本発明の一実施例の工程順模式断面図
である。図において，７はSiO2膜，８はZr膜, ９は ZrN
膜, 10は第１のレジスト膜，11はNb膜, 12は第２のレジ
スト膜，13はSi基板, 14はAl-AlOX 膜である。FIG. 2 is a schematic sectional view in order of the steps of an embodiment of the present invention. In the figure, 7 is a SiO 2 film, 8 is a Zr film, and 9 is ZrN.
A film, 10 is a first resist film, 11 is a Nb film, 12 is a second resist film, 13 is a Si substrate, and 14 is an Al—AlO X film.
【００２１】図２（ａ）に示すように，ジョセフソン集
積回路形成用のSi基板に形成されたSiO2膜７上に先ずZr
膜８をDCマグネトロンスパッタにより 1,000Åの厚さに
堆積する。Ar圧力 1.3Pa, 印加電力 300Ｗ，印加電流
1.0Ａ，堆積速度 100Å／minである。As shown in FIG. 2A, first, Zr is formed on the SiO 2 film 7 formed on the Si substrate for forming the Josephson integrated circuit.
Film 8 is deposited by DC magnetron sputtering to a thickness of 1,000Å. Ar pressure 1.3Pa, Applied power 300W, Applied current
1.0A, deposition rate is 100Å / min.
【００２２】続いて, ＲＦマグネトロンスパッタにより
ZrN の反応性スパッタを行い, 100Åの厚さにZr膜８上
に積層する。Ar圧力 2.0Pa, N2圧力 0.2Pa, 印加電力 4
00Ｗ，堆積速度30Å／min である。Then, by RF magnetron sputtering
Reactive sputtering of ZrN is performed to deposit 100 Å thickness on the Zr film 8. Ar pressure 2.0Pa, N 2 pressure 0.2Pa, Applied power 4
It is 00W and the deposition rate is 30Å / min.
【００２３】抵抗体形成領域に通常のフォトリソグラフ
ィにより, 第１のレジスト膜10をパターニングする。図
２（ｂ）に示すように，第１のレジスト膜10をマスクと
して, イオンビームエッチング（ＩＢＥ）により，ZrN
膜９とZr膜８のエッチングを行い, 抵抗体パターンを形
成する。The first resist film 10 is patterned in the resistor formation region by ordinary photolithography. As shown in FIG. 2 (b), the first resist film 10 is used as a mask to perform ZrN etching by ion beam etching (IBE).
The film 9 and the Zr film 8 are etched to form a resistor pattern.
【００２４】ＲＩＥによるエッチングでは ZrN膜９のエ
ッチングはできるが，Zr膜８のエッチングができないた
めに，ＩＢＥ法を用いる。エッチング条件は，Ar圧力
0.1Pa加速電圧 350Ｗ，エッチング速度 100Å／min で
ある。Although the ZrN film 9 can be etched by RIE etching, the IBE method is used because the Zr film 8 cannot be etched. Etching conditions are Ar pressure
Acceleration voltage of 0.1Pa is 350W and etching rate is 100Å / min.
【００２５】図２（ｃ）に示すように，第１のレジスト
膜10を除去した後, 配線層の超伝導体膜であるNb膜11を
Si基板上全面にDCマグネトロンスパッタにより 3,000Å
の厚さに被覆する。成膜条件は，Ar圧力 1.3Pa, 印加電
圧 300Ｗ，印加電流 2.0Ａ，堆積速度 300Å／min であ
る。As shown in FIG. 2C, after removing the first resist film 10, the Nb film 11 which is a superconductor film of the wiring layer is removed.
3,000Å by DC magnetron sputtering on the entire surface of Si substrate
To the thickness of. The film forming conditions are Ar pressure of 1.3 Pa, applied voltage of 300 W, applied current of 2.0 A, and deposition rate of 300 Å / min.
【００２６】図２（ｄ）に示すように，通常のフォトリ
ソグラフィにより, 第２のレジスト膜10をパターニング
した後，第２のレジスト膜10をマスクとして, Nb膜11を
ＲＩＥによりエッチングして配線層を形成する。反応ガ
スとして, CF4+O2の混合ガスを用い, 真空度８Pa, 印加
電力50Ｗで行う。As shown in FIG. 2D, after patterning the second resist film 10 by ordinary photolithography, the Nb film 11 is etched by RIE using the second resist film 10 as a mask to form wiring. Form the layers. A mixed gas of CF 4 + O 2 is used as a reaction gas, the degree of vacuum is 8 Pa, and the applied power is 50 W.
【００２７】この時, 同時に, Zr膜８の抵抗体パターン
の両端に当たる ZrN膜９の, Zr膜８とNb膜11の接続部を
残して, Zr膜８上の ZrN膜９もＲＩＥによりエッチング
されるが, Zr膜８はエッチングされていでそのまま抵抗
体として残る。At this time, at the same time, the ZrN film 9 on the Zr film 8 is also etched by RIE, leaving the connecting portions of the Zr film 8 and the Nb film 11 of the ZrN film 9 which correspond to both ends of the resistor pattern of the Zr film 8. However, the Zr film 8 remains as a resistor because it is etched.
【００２８】図２（ｅ）に示すように，第２のレジスト
膜12を除去してジョセフソン集積回路の抵抗体の形成を
完了する。実施例では, 本発明に係るジョセフソン集積
回路の抵抗体の領域部分についてのみ, 製造工程を説明
したが, ジョセフソン集積回路のジョセフソン接合部も
同時に並行して製造されるため, 完成品は図２（ｆ）に
示したものとなる。As shown in FIG. 2E, the second resist film 12 is removed to complete the formation of the resistor of the Josephson integrated circuit. In the example, the manufacturing process was described only for the region part of the resistor of the Josephson integrated circuit according to the present invention, but since the Josephson junction part of the Josephson integrated circuit is also manufactured in parallel, the finished product is It becomes what was shown in FIG.2 (f).
【００２９】[0029]
【発明の効果】以上説明したように，本発明によれば，
抵抗体の遷移金属膜堆積時には遷移金属膜と遷移金属窒
化膜との二層構造となるが，超伝導体膜の配線層のパタ
ーニング時には超伝導体膜の配線層と抵抗体の接続部の
みが二層構造として残り，他の抵抗体の部分は遷移金属
の一層構造となる。As described above, according to the present invention,
When the transition metal film of the resistor is deposited, it has a two-layer structure of the transition metal film and the transition metal nitride film, but when patterning the wiring layer of the superconductor film, only the connecting portion between the wiring layer of the superconductor film and the resistor is formed. It remains as a two-layer structure, and the other resistor part has a single-layer structure of transition metal.
【００３０】遷移金属窒化物は安定で表面が酸化されな
いために，超伝導体膜の堆積前にArによるエッチング処
理を行う必要がない。遷移金属窒化膜は安定なため, 超
伝導体膜と遷移金属抵抗体との間のバリアとして有効で
あり, 拡散が素子され, 熱的に安定となる。Since the transition metal nitride is stable and its surface is not oxidized, it is not necessary to perform an etching treatment with Ar before depositing the superconductor film. Since the transition metal nitride film is stable, it is effective as a barrier between the superconducting film and the transition metal resistor, and diffusion is made into an element, which makes it thermally stable.
【００３１】SiO の蒸着工程が不要となりプロセスの簡
単化が図れる。上記の効果により, 本発明はジョセフソ
ン集積回路の製造において, 品質ならびに信頼性の向
上, コストダウンの改善に大きく寄与することとなる。The process of vapor deposition of SiO 2 is unnecessary and the process can be simplified. Due to the above effects, the present invention greatly contributes to improvement of quality and reliability and cost reduction in manufacturing Josephson integrated circuits.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 本発明の一実施例の工程順模式断面図FIG. 2 is a schematic cross-sectional view in order of the processes of an embodiment of the present invention.
【図３】 従来例の説明図FIG. 3 is an explanatory diagram of a conventional example.
１ 絶縁膜 ２ 遷移金属膜 ３ 遷移金属窒化膜 ４ 第１のレジスト膜 ５ 超伝導体膜 ６ 第２のレジスト膜 ７ SiO2膜 ８ Zr膜 ９ ZrN膜 10 第１のレジスト膜 11 Nb膜 12 第２のレジスト膜 13 Si基板 14 Al-AlOX 膜1 Insulating Film 2 Transition Metal Film 3 Transition Metal Nitride Film 4 First Resist Film 5 Superconductor Film 6 Second Resist Film 7 SiO 2 Film 8 Zr Film 9 ZrN Film 10 First Resist Film 11 Nb Film 12 Second 2 resist film 13 Si substrate 14 Al-AlO X film
Claims (3)
伝導体膜(5) のパターン形成時にエッチングストッパと
なる遷移金属(2) からなり，該遷移金属(2)と該超伝導
体膜(5) との接続部において，該遷移金属(2) は該遷移
金属窒化物(3) を介して該超伝導体膜(5) と接続してな
ることを特徴とするジョセフソン集積回路用抵抗体。1. The resistor pattern on the insulating film (1) comprises a transition metal (2) which serves as an etching stopper during pattern formation of the superconductor film (5). The Josephson integrated device characterized in that the transition metal (2) is connected to the superconductor film (5) through the transition metal nitride (3) at the connection portion with the body film (5). Circuit resistor.
は，ハフニウムからなり，前記遷移金属窒化物は窒化ジ
ルコニウ, 或いは, 窒化ハウニウムからなることを特徴
とする請求項１記載のジョセフソン集積回路用抵抗体。2. The Josephson integrated circuit according to claim 1, wherein the transition metal (2) is made of zirconium or hafnium, and the transition metal nitride is made of zirconium nitride or hanium nitride. Resistor.
窒化物(3) を順次,積層する工程と， 該遷移金属窒化物(3) と該遷移金属(2) を第１のレジス
ト膜(4) をマスクとして, 抵抗体パターンにエッチング
する工程と, 該遷移金属窒化物(3) と該遷移金属(2) を覆って超伝導
体膜(5) を被覆する工程と, 第２のレジスト膜(6) をマスクとして, 抵抗パターンの
両端に当たる該遷移金属窒化膜(3) の該遷移金属膜(2)
と該超伝導体膜(5) の接続部を残して, 該遷移金属窒化
膜(3) をエッチングする工程とを含むことを特徴とする
ジョセフソン集積回路用抵抗体の製造方法。3. A step of sequentially laminating a transition metal (2) and a transition metal nitride (3) on an insulating film (1), and a step of depositing the transition metal nitride (3) and the transition metal (2). A step of etching the resistor pattern using the resist film (4) of No. 1 as a mask; and a step of covering the transition metal nitride (3) and the transition metal (2) with a superconductor film (5). Then, using the second resist film (6) as a mask, the transition metal film (2) of the transition metal nitride film (3) hitting both ends of the resistance pattern
And a step of etching the transition metal nitride film (3) while leaving the connection portion of the superconductor film (5), the method for manufacturing a resistor for a Josephson integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4008812A JPH05198851A (en) | 1992-01-22 | 1992-01-22 | Resistor for josephson integrated circuit and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4008812A JPH05198851A (en) | 1992-01-22 | 1992-01-22 | Resistor for josephson integrated circuit and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05198851A true JPH05198851A (en) | 1993-08-06 |
Family
ID=11703239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4008812A Withdrawn JPH05198851A (en) | 1992-01-22 | 1992-01-22 | Resistor for josephson integrated circuit and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05198851A (en) |
-
1992
- 1992-01-22 JP JP4008812A patent/JPH05198851A/en not_active Withdrawn
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4589961A (en) | Aluminum mask anodization with lift-off for patterning Josephson junction devices | |
| JPH05198851A (en) | Resistor for josephson integrated circuit and its manufacture | |
| JP2535539B2 (en) | Josephson circuit manufacturing method | |
| JPS61208879A (en) | Manufacture of josephson integrated circuit | |
| JPH0260230B2 (en) | ||
| JPS60208873A (en) | Manufacture of josephson junction element | |
| JPH05175562A (en) | Manufacture of josephson ic | |
| JPS63224273A (en) | Josephson junction element and its manufacture | |
| JP2003198007A (en) | Method of forming tunnel junction and tunnel junction device | |
| JPS61263179A (en) | Manufacture of josephson junction element | |
| JPS63192283A (en) | Formation of superconducting line | |
| JPS6135577A (en) | Josephson junction element | |
| JPS61115360A (en) | Manufacture of josephson integrated circuit | |
| JPS61244078A (en) | Manufacture of superconducting lines | |
| JPH03135071A (en) | Thin film transistor and manufacture thereof | |
| JPH0661535A (en) | Manufacture of josephson circuit | |
| JPH03263884A (en) | Manufacture of josephson integrated circuit | |
| JPH06132576A (en) | Manufacture of superconducting element | |
| JPH0634417B2 (en) | Method for manufacturing josephson junction device | |
| JPH0613672A (en) | Manufacture of josephson junction device | |
| JPH0379875B2 (en) | ||
| JPS62173776A (en) | Manufacture of josephson junction element | |
| JPH03219680A (en) | Manufacture of josephson junction | |
| JPH0812939B2 (en) | Method for manufacturing jjosephson integrated circuit | |
| JPH077189A (en) | Josephson junction element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990408 |