JPH0379875B2 - - Google Patents
Info
- Publication number
- JPH0379875B2 JPH0379875B2 JP61229533A JP22953386A JPH0379875B2 JP H0379875 B2 JPH0379875 B2 JP H0379875B2 JP 61229533 A JP61229533 A JP 61229533A JP 22953386 A JP22953386 A JP 22953386A JP H0379875 B2 JPH0379875 B2 JP H0379875B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resistor
- superconductor
- wiring
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002887 superconductor Substances 0.000 claims description 52
- 238000005530 etching Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 239000007789 gas Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 16
- 230000001681 protective effect Effects 0.000 description 10
- 239000010955 niobium Substances 0.000 description 6
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 5
- 229910001882 dioxygen Inorganic materials 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】
〔概要〕
ジヨセフソン集積回路の抵抗体の製造方法であ
つて、絶縁膜を形成した半導体基板上に抵抗体と
この抵抗体とエツチング速度の異なる超伝導体層
を同一真空糟内で連続的に積層形成後、この超伝
導体層と抵抗体層を所定のパターンにエツチング
する。[Detailed Description of the Invention] [Summary] A method for manufacturing a resistor for a Josephson integrated circuit, in which a resistor and a superconductor layer having different etching rates are etched on a semiconductor substrate on which an insulating film is formed in the same vacuum. After successively forming layers in a chamber, the superconductor layer and resistor layer are etched into a predetermined pattern.
次いでこの超伝導体層と同一の材料よりなる配
線用の超伝導体層を被着し、この配線用超伝導体
層、およびその下の超伝導体層を抵抗体層の表面
が露出する迄エツチングすることで、抵抗体層と
配線用超伝導体層の間の接触抵抗を無くし、かつ
抵抗体層とその上に形成する超伝導体層とを、エ
ツチング速度の異なる材料を用いることでガスエ
ツチングで容易に抵抗体の形状が高精度に得られ
るようにしたもの。 Next, a superconductor layer for wiring made of the same material as this superconductor layer is deposited, and this superconductor layer for wiring and the superconductor layer below it are coated until the surface of the resistor layer is exposed. By etching, the contact resistance between the resistor layer and the wiring superconductor layer is eliminated, and the resistor layer and the superconductor layer formed thereon are etched using materials with different etching rates. The shape of the resistor can be easily obtained with high precision through etching.
本発明は半導体装置の製造方法に係り、特にジ
ヨセフソン集積回路の抵抗体の製造方法に関す
る。
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a resistor of a Josephson integrated circuit.
絶縁膜を形成した半導体基板上に、ジヨセフソ
ン接合、抵抗体および超伝導体配線層を設けたジ
ヨセフソン集積回路は、極低温時に於いて超高速
性、低消費電力で動作するため、電子計算機に用
いる素子として注目されている。 Josephson integrated circuits, which have Josephson junctions, resistors, and superconductor wiring layers on a semiconductor substrate with an insulating film, are used in electronic computers because they operate at ultrahigh speeds and with low power consumption at extremely low temperatures. It is attracting attention as an element.
このようなジヨセフソン集積回路に用いる抵抗
体としては、超伝導体配線層との接触部分に於け
る接触抵抗の低下、およびこの抵抗体が高精度に
工程を簡略化した状態で所定のパターンに形成さ
れることが要望されている。 The resistors used in such Josephson integrated circuits are designed to reduce the contact resistance at the contact area with the superconductor wiring layer, and to form the resistors into a predetermined pattern with high precision and a simplified process. It is requested that this be done.
従来のこのようなジヨセフソン集積回路の抵抗
体の製造方法に付いて第２図ａより第２図ｆ迄を
用いて説明する。
A conventional method of manufacturing a resistor for a Josephson integrated circuit will be explained with reference to FIGS. 2a to 2f.
第２図ａに示すように、Si基板１上にSiO2膜
よりなる絶縁膜２を形成後、その上に抵抗体とし
てのモリブデン（Mo）膜よりなる抵抗体層３
を、スパツタ法を用いて形成する。 As shown in FIG. 2a, after forming an insulating film 2 made of a SiO 2 film on a Si substrate 1, a resistor layer 3 made of a molybdenum (Mo) film as a resistor is formed thereon.
is formed using a sputtering method.
次いで第２図ｂに示すように、該抵抗体層３上
に所定パターンのレジスト膜４を形成後、このレ
ジスト膜４をマスクとして用い、四弗化炭素
（CH4）ガスと酸素ガスの混合ガスで、酸素ガス
が全体の容量の５％添加されたガスを反応ガスと
して用いた、リアクテイブイオンエツチング（以
下RIE法と称する）法を用いてMo膜３を所定の
パターンにエツチングする。 Next, as shown in FIG. 2b, after forming a resist film 4 in a predetermined pattern on the resistor layer 3, using this resist film 4 as a mask, carbon tetrafluoride (CH 4 ) gas and oxygen gas are mixed. The Mo film 3 is etched into a predetermined pattern using a reactive ion etching (hereinafter referred to as RIE method) method using a gas to which 5% of the total volume of oxygen gas is added as a reactive gas.
次いで第２図ｃに示すように、前記したレジス
ト膜４を除去した後、前記所定のパターンに形成
された抵抗体層３を含む基板１上に所定パターン
のレジスト膜５を形成する。 Next, as shown in FIG. 2c, after removing the resist film 4 described above, a resist film 5 having a predetermined pattern is formed on the substrate 1 including the resistor layer 3 formed in the predetermined pattern.
このレジスト膜５は、抵抗体層３が、後の工程
で超伝導体の配線層と接続される箇所を被覆する
ように設ける。 This resist film 5 is provided so as to cover a portion where the resistor layer 3 will be connected to a superconductor wiring layer in a later step.
更に該基板にSiO膜より成る保護膜６を蒸着に
より形成する。この保護膜６は後の工程で超伝導
体の配線層をエツチングする際に、抵抗体となる
Mo膜３の表面を損傷しないようにするための保
護膜として設ける。 Furthermore, a protective film 6 made of a SiO film is formed on the substrate by vapor deposition. This protective film 6 becomes a resistor when etching the superconductor wiring layer in a later process.
It is provided as a protective film to prevent the surface of the Mo film 3 from being damaged.
次いでリフトオフ法によりレジスト膜５を除去
すると共に、その上の不要なSiO膜６をも除去す
る。 Next, the resist film 5 is removed by a lift-off method, and the unnecessary SiO film 6 thereon is also removed.
次いで第２図ｄに示すように、保護膜６が被覆
されていない抵抗体層３の部分は、後の工程で超
伝導体より成る配線層が接続される箇所であるの
で、その部分をArガスを用いてスパツタリング
を行いその抵抗体層３の表面に形成されている酸
化膜等を除去する。 Next, as shown in FIG. 2d, the portion of the resistor layer 3 that is not covered with the protective film 6 is connected to a wiring layer made of a superconductor in a later step, so that portion is coated with Ar. Sputtering is performed using gas to remove the oxide film and the like formed on the surface of the resistor layer 3.
次いで第２図ｅに示すように、該基板上にニオ
ブ（Nb）より成る配線用超伝導体層７を形成後、
抵抗体層３を所定のパターンに形成するためのマ
スクとなるレジスト膜８を所定のパターンに形成
して被覆する。 Next, as shown in FIG. 2e, after forming a wiring superconductor layer 7 made of niobium (Nb) on the substrate,
A resist film 8 serving as a mask for forming the resistor layer 3 in a predetermined pattern is formed in a predetermined pattern and covered.
次いで第２図ｆに示すように、前記したレジス
ト膜８をマスクとして用いてRIE法により配線用
の超伝導体層７を所定のパターンに形成してジヨ
セフソン集積回路の抵抗体を製造していた。 Next, as shown in FIG. 2f, a superconductor layer 7 for wiring was formed in a predetermined pattern by the RIE method using the resist film 8 as a mask to manufacture a resistor for a Josephson integrated circuit. .
然し、従来のジヨセフソン集積回路の抵抗体の
製造に於いては、その上に形成される超伝導体の
配線層との接触領域の酸化膜を除去するための
Arガスのスパツタエツチングを行う際のSiOより
成る保護膜６や、配線層７を所定のパターンに形
成する際のRIE法に於いて、抵抗体層３の表面が
損傷されないようにするための保護膜としての
SiO膜６を形成する余分な工程が必要で、この工
程を行うために基板を真空糟より取り出して、別
個の真空糟に移動される間に、その抵抗体層３の
表面が空気に曝されて酸化する問題が生じる。
However, in the production of conventional resistors for Josephson integrated circuits, it is necessary to remove the oxide film in the contact area with the superconductor wiring layer formed thereon.
In order to prevent the surface of the resistor layer 3 from being damaged during the RIE method when forming the protective film 6 made of SiO during Ar gas sputter etching and when forming the wiring layer 7 into a predetermined pattern, as a protective film
An extra step is required to form the SiO film 6, and for this step the surface of the resistor layer 3 is exposed to air while the substrate is taken out of the vacuum chamber and transferred to a separate vacuum chamber. This causes the problem of oxidation.
本発明は上記した問題点を除去し、抵抗体層と
超伝導体層との接触部分で酸化膜が形成されない
ようにし、かつ抵抗体層の表面を保護する保護膜
のような余分な工程を必要としなくて、抵抗体層
が所定のパターンに高精度に、工程を簡略化した
状態で得られるようにしたジヨセフソン集積回路
の抵抗体の提供を目的とする。 The present invention eliminates the above-mentioned problems, prevents the formation of an oxide film at the contact area between the resistor layer and the superconductor layer, and eliminates extra steps such as a protective film to protect the surface of the resistor layer. An object of the present invention is to provide a resistor for a Josephson integrated circuit, in which a resistor layer can be obtained in a predetermined pattern with high precision and with simplified steps without requiring the resistor layer.
本発明のジヨセフソン集積回路の抵抗体の製造
方法は、絶縁膜を形成した半導体基板上に抵抗体
層と、該抵抗体層とエツチング速度の異なる超伝
導体層を連続的に積層形成する工程、
該超伝導体層の上に所定のパターンのレジスト
膜を形成後、該レジスト膜をマスクとして超伝導
体層および抵抗体層を所定のパターンにエツチン
グする工程、
前記レジスト膜を除去後、所定のパターンに形
成された超伝導体層と抵抗体層上に配線用の超伝
導体層を被着形成する工程、
該配線用の超伝導体層上に所定パターンのレジ
スト膜を形成後、該レジスト膜をマスクとして配
線用の超伝導体層、並びにその下の所定パターン
に形成された超伝導体層をエツチングして配線用
の超伝導体層と接続された抵抗体を形成する。
A method for manufacturing a resistor for a Josephson integrated circuit according to the present invention includes the steps of successively stacking a resistor layer and a superconductor layer having an etching rate different from that of the resistor layer on a semiconductor substrate on which an insulating film is formed; After forming a resist film with a predetermined pattern on the superconductor layer, etching the superconductor layer and the resistor layer into a predetermined pattern using the resist film as a mask; After removing the resist film, etching the resist film with a predetermined pattern. A step of depositing a superconductor layer for wiring on the superconductor layer and resistor layer formed in a pattern, after forming a resist film of a predetermined pattern on the superconductor layer for wiring, Using the film as a mask, the superconductor layer for wiring and the superconductor layer formed in a predetermined pattern thereunder are etched to form a resistor connected to the superconductor layer for wiring.
本発明は抵抗体層の上に該抵抗体層とは同一の
エツチングガスによつて侵されない超伝導体層を
連続的に真空糟より出し入れしない状態で連続的
に成膜し、この超伝導体層の一部に超伝導体配線
層を形成することで、配線層と抵抗体層との接触
抵抗を無くする。
In the present invention, a superconductor layer that is not eroded by the same etching gas as the resistor layer is continuously formed on the resistor layer without being taken in or out of a vacuum chamber, and this superconductor layer is By forming a superconductor wiring layer in a part of the layer, contact resistance between the wiring layer and the resistor layer is eliminated.
また超伝導体配線層と抵抗体層とは同一のエツ
チングガスを用いた時に、エツチング速度の異な
る材料を用いているので、超伝導体配線層を所定
のパターンにエツチングする際に抵抗体層の表面
を損傷しない状態で、エツチングできるので、抵
抗体層の表面にエツチングの際の保護膜を形成す
るような余分な工程を必要としないで簡略化され
た工程で、抵抗体層が所定の形状に高精度に形成
できる。 Furthermore, when the same etching gas is used for the superconductor wiring layer and the resistor layer, materials with different etching rates are used, so when etching the superconductor wiring layer into a predetermined pattern, the resistor layer is Since etching can be performed without damaging the surface, the resistor layer can be formed into a predetermined shape using a simplified process that does not require an extra step such as forming a protective film on the surface of the resistor layer during etching. It can be formed with high precision.
以下、図面を用いて本発明の一実施例につき詳
細に説明する。
Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図ａに示すように、スパツタ法を用いて形
成したSiO2膜、或いは蒸着法を用いて形成した
SiO膜のような絶縁膜１２を有するSi基板１１上
に、厚さが10nm（ナノメータ）程度の、アルミニ
ウム（Al）、或いはチタン（Ti）等よりなる抵抗
体層１３、および厚さが10nmのNbよりなる超伝
導体層１４を同一の真空糟を用いて、真空を破る
ことなく連続的にスパツタ法を用いて成膜する。 As shown in Figure 1a, the SiO 2 film formed using the sputtering method or the SiO 2 film formed using the vapor deposition method
On a Si substrate 11 having an insulating film 12 such as a SiO film, there is a resistor layer 13 made of aluminum (Al), titanium (Ti), etc. with a thickness of about 10 nm (nanometers), and a resistor layer 13 with a thickness of about 10 nm (nanometers). A superconductor layer 14 made of Nb is continuously formed using the same vacuum chamber by sputtering without breaking the vacuum.
ここでAlやTiよりなる抵抗体層１３は、Nbよ
りなる超伝導体層１４のエツチングガスによつて
殆ど侵されず、また抵抗体層１３と超伝導体層１
４は連続的に真空を破らずに成膜されているた
め、その間で表面酸化による接触抵抗が発生する
ことがない。 Here, the resistor layer 13 made of Al or Ti is hardly attacked by the etching gas of the superconductor layer 14 made of Nb, and the resistor layer 13 and the superconductor layer
Since the film No. 4 is formed continuously without breaking the vacuum, contact resistance due to surface oxidation does not occur between the films.
次いで第１図ｂに示すように、該基板を真空糟
より取り出した後、所定の抵抗体のパターンに対
応するような形状のレジスト膜１５をホトリソグ
ラフイ法を用いて形成する。 Next, as shown in FIG. 1B, after the substrate is removed from the vacuum chamber, a resist film 15 having a shape corresponding to a predetermined resistor pattern is formed using photolithography.
次いでこのレジスト膜１５をマスクとして用い
て、その下のNbよりなる超伝導体層１４を、反
応ガスとして四弗化炭素（CF4）ガスと酸素ガス
の混合ガスで酸素ガスが全体の容量の５％添加さ
れたガスを用い、ガスの圧力を13Pa（パスカル）
とし、高周波発振動機に印加される電力を50Wと
した条件でエツチングする。 Next, using this resist film 15 as a mask, the superconductor layer 14 made of Nb under it is heated with a mixed gas of carbon tetrafluoride (CF 4 ) gas and oxygen gas as a reactive gas, so that the oxygen gas occupies the entire capacity. Using 5% added gas, the gas pressure was set to 13Pa (Pascal).
Etching is performed under the condition that the power applied to the high-frequency oscillator is 50W.
またその下のAlよりなる抵抗体層１３を、Ar
ガスを0.5Paの圧力で真空糟内に導入し、印加電
力を100Wの印加電力とした条件でエツチングす
る。 In addition, the resistor layer 13 made of Al under it is
Etching is performed under the conditions that gas is introduced into the vacuum chamber at a pressure of 0.5 Pa and the applied power is 100 W.
次いで第１図ｃに示すように、前記レジスト膜
１５を除去した後、超伝導体層１４の表面をAr
ガスを0.5Paの圧力、印加電圧を200Vとした条件
でエツチングし、その表面をクリーニングする。 Next, as shown in FIG. 1c, after removing the resist film 15, the surface of the superconductor layer 14 is heated with Ar.
Etching is performed using gas at a pressure of 0.5 Pa and an applied voltage of 200 V to clean the surface.
次いで該基板上にNbよりなる配線用超伝導体
層１６を前記したスパツタ法で堆積する。 Next, a wiring superconductor layer 16 made of Nb is deposited on the substrate by the sputtering method described above.
更にこの配線用超伝導体層を所定のパターンに
成形するためのレジスト膜１７をホトリソグラフ
イ法を用いて所定のパターンに形成する。 Furthermore, a resist film 17 for forming the superconductor layer for wiring into a predetermined pattern is formed into a predetermined pattern using photolithography.
次いで第１図ｄに示すように、このレジスト膜
１７をマスクとして用い、反応ガスをCF4ガスと
酸素の混合ガスで酸素ガスが全体の５容量％含有
されている混合ガスを用いて、このガス圧を
13Pa、高周波発振機の印加電力を50Wとした条
件でRIE法によりエツチングする。 Next, as shown in FIG. 1d, this resist film 17 is used as a mask, and a mixed gas of CF 4 gas and oxygen containing 5% by volume of the total oxygen gas is used as the reaction gas. gas pressure
Etching is carried out by the RIE method under conditions of 13 Pa and the applied power of the high frequency oscillator of 50 W.
このエツチングの過程で、抵抗体層となるAl
膜、或いはTi膜は、前記した反応ガスによつて
エツチングされないため、従来の方法で必要とし
たSiO膜の保護膜は必要とせず、その分だけ工程
が簡単になる。 During this etching process, the Al that will become the resistor layer is etched.
Since the film or the Ti film is not etched by the above-mentioned reaction gas, the protective film of SiO film required in the conventional method is not required, and the process is simplified accordingly.
また抵抗体層１３の上に設けた超伝導体層１４
の上に、これと同一材料の配線用超伝導体層１６
を設けているので、配線層と抵抗体層の間に接触
抵抗が発生するおそれもなくなる。 In addition, a superconductor layer 14 provided on the resistor layer 13
On top of this, a wiring superconductor layer 16 made of the same material as this
Therefore, there is no possibility that contact resistance will occur between the wiring layer and the resistor layer.
以上述べたように、本発明のジヨセフソン集積
回路の抵抗体の製造方法によれば、抵抗体と配線
用超伝導体層の間に接触抵抗が発生せず、また配
線層を所定のパターンに形成する際に抵抗体の表
面に保護膜を必要としないため、高信頼度のジヨ
セフソン集積回路が、工程を簡単にした状態で容
易に形成できる効果がある。
As described above, according to the method of manufacturing a resistor for a Josephson integrated circuit of the present invention, contact resistance does not occur between the resistor and the wiring superconductor layer, and the wiring layer is formed in a predetermined pattern. Since no protective film is required on the surface of the resistor, a highly reliable Josephson integrated circuit can be easily formed with a simple process.
第１図ａより第１図ｄ迄は本発明の製造方法の
工程の一実施例を示す断面図、第２図ａより第２
図ｆ迄は従来の製造方法の工程を説明するための
断面図である。
図に於いて、１１はSf基板、１２は絶縁膜、１
３は抵抗体層、１４は超伝導体層、１５，１７は
レジスト膜、１６は配線用超伝導体層を示す。
1a to 1d are cross-sectional views showing one embodiment of the process of the manufacturing method of the present invention, and FIGS.
The figures up to FIG. f are sectional views for explaining the steps of the conventional manufacturing method. In the figure, 11 is an Sf substrate, 12 is an insulating film, 1
3 is a resistor layer, 14 is a superconductor layer, 15 and 17 are resist films, and 16 is a wiring superconductor layer.
Claims (1)
抗体層１３と、該抵抗体層１３とエツチング速度
の異なる超伝導体層１４を連続的に積層形成する
工程、 該超伝導体層１４の上に所定のパターンのレジ
スト膜１５を形成後、該レジスト膜１５をマスク
として超伝導体層１４および抵抗体層１３を所定
のパターンにエツチングする工程、 前記レジスト膜１５を除去後、所定のパターン
に形成された超伝導体層１４と抵抗体層１３上に
配線用の超伝導体層１６を被着形成する工程、 該配線用の超伝導体層１６上に所定パターンの
レジスト膜１７を形成後、該レジスト膜１７をマ
スクとして配線用の超伝導体層１６、並びにその
下の所定パターンに形成された超伝導体層１４を
エツチングして配線用の超伝導体層１６と接続さ
れた抵抗体層１３を形成することを特徴とするジ
ヨセフソン集積回路の抵抗体の製造方法。[Scope of Claims] 1. A step of successively laminating a resistor layer 13 and a superconductor layer 14 having an etching rate different from that of the resistor layer 13 on a semiconductor substrate 11 on which an insulating film 12 is formed. After forming a resist film 15 in a predetermined pattern on the conductor layer 14, etching the superconductor layer 14 and the resistor layer 13 into a predetermined pattern using the resist film 15 as a mask; removing the resist film 15; After that, a step of forming a superconductor layer 16 for wiring on the superconductor layer 14 and the resistor layer 13 formed in a predetermined pattern, and forming a superconductor layer 16 for wiring in a predetermined pattern on the superconductor layer 16 for wiring. After forming the resist film 17, the superconductor layer 16 for wiring and the superconductor layer 14 formed in a predetermined pattern thereunder are etched using the resist film 17 as a mask to form the superconductor layer 16 for wiring. 1. A method of manufacturing a resistor for a Josephson integrated circuit, comprising forming a resistor layer 13 connected to a resistor layer 13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61229533A JPS6386487A (en) | 1986-09-30 | 1986-09-30 | Manufacture of resistor for josephson integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61229533A JPS6386487A (en) | 1986-09-30 | 1986-09-30 | Manufacture of resistor for josephson integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6386487A JPS6386487A (en) | 1988-04-16 |
| JPH0379875B2 true JPH0379875B2 (en) | 1991-12-20 |
Family
ID=16893658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61229533A Granted JPS6386487A (en) | 1986-09-30 | 1986-09-30 | Manufacture of resistor for josephson integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6386487A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63234533A (en) * | 1987-03-24 | 1988-09-29 | Agency Of Ind Science & Technol | Formation of josephson junction element |
-
1986
- 1986-09-30 JP JP61229533A patent/JPS6386487A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6386487A (en) | 1988-04-16 |
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| EXPY | Cancellation because of completion of term |