JPH04365340A - 複合回路型半導体装置 - Google Patents

複合回路型半導体装置

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Publication number
JPH04365340A
JPH04365340A JP3141600A JP14160091A JPH04365340A JP H04365340 A JPH04365340 A JP H04365340A JP 3141600 A JP3141600 A JP 3141600A JP 14160091 A JP14160091 A JP 14160091A JP H04365340 A JPH04365340 A JP H04365340A
Authority
JP
Japan
Prior art keywords
circuit pattern
semiconductor device
type semiconductor
bumps
connection part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3141600A
Other languages
English (en)
Inventor
Hideyuki Ichiyama
一山 秀之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3141600A priority Critical patent/JPH04365340A/ja
Publication of JPH04365340A publication Critical patent/JPH04365340A/ja
Pending legal-status Critical Current

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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】
【0001】
【産業上の利用分野】本発明は、複合回路型半導体装置
の構造に関する。
【0002】
【従来の技術】図3は従来の複合回路型半導体装置の全
体斜視図であり、同図において、1はセラミック等の絶
縁性材料からなる絶縁基板、2はこの絶縁基板1の表面
に形成されている回路パターン、3は表面に集積回路が
形成され、裏面を接着剤7で回路パターン2上に固着さ
れている半導体素子、4はこの半導体素子3の電極と回
路パターン2を接続している金属細線、5は回路パター
ン2とはんだ等で接続されており、外部と電気信号のや
りとりを行う外部リードである。そして、基板1に搭載
された半導体素子3および接続線である金属細線4は、
これを保護する目的で、図4および図5に示すように、
ポッティング樹脂16等により基板1上にコーティング
される。このコーティングは図4に示すように部分的に
行う場合もあり、また全体的に行う場合もある。また、
半導体素子3を基板1に搭載する方法としては、図6に
示すように、半導体素子3の集積回路が形成されている
面と、基板1の回路パターン2が形成されている面とを
向かい合わせ、半導体素子3上の電極8と回路パターン
2をバンプ9により接続する方法もある。
【0003】
【発明が解決しようとする課題】従来の複合回路型半導
体装置は以上のように構成されているので、基板上の一
部分あるいは全面的にポッティング樹脂等でコーティン
グしなければならず、液状の樹脂を滴下させるという工
程が必要で、生産性や製品となった後の信頼性に問題が
あった。また、外部リードは基板にはんだ付け等で接続
されているので、リード間に一定以上の間隔を確保しな
ければならず端子の数が増えると基板面積が大きくなっ
てしまう等の問題点があった。この発明は上記のような
問題点を解消するためになされたもので、複合回路型半
導体装置を小型化できるとともに、半導体素子から外部
リードまでの距離が非常に短縮され、かつ高周波特性の
よい銅箔等が使用可能とし、電気的ノイズが少なく、応
答速度も早く、さらに信頼性も高い複合回路型半導体装
置を得ることを目的とする。
【0004】
【課題を解決するための手段】この目的を達成するため
に、この発明に係る複合回路型半導体装置は、絶縁性材
料からなり表面に回路パターンが形成された基板と、こ
の基板に搭載され前記回路パターンの一方の接続部と電
気的に接続された電極を有する複数の半導体素子と、前
記回路パターンの他方の接続部と電気的に接続された外
部リードとからなり、前記回路パターンの他方の接続部
および外部リードの接続部に金あるいははんだでバンプ
を形成し、これらバンプ間を銅箔を表面に有するテープ
で接続し、全体を封止樹脂で成形加工したものである。 また、本発明に係る複合回路型半導体装置は、絶縁性材
料からなり表面に回路パターンが形成された基板と、こ
の基板に搭載され前記回路パターンの一方の接続部と電
気的に接続された電極を有する複数の半導体素子と、前
記回路パターンの他方の接続部と電気的に接続された外
部リードとからなり、前記回路パターンの他方の接続部
に金あるいははんだでバンプを形成し、このバンプに銅
、金あるいはアルミニウムからなる金属細線の一方を合
金形成により接続するとともに、金属細線の他方を前記
外部リードに圧接あるいは圧着により接続し、全体を封
止樹脂で成形加工したものである。
【0005】
【作用】この発明における外部リードと回路パターンと
の接続はバンプと銅箔の組合わせによるもであり、電気
的特性が良好である。また、この発明における外部リー
ドへの接続はテープあるいは金属細線によるものであり
、端子数の増加に対しても基板面積をさほど大きくする
必要がない。
【0006】
【実施例】以下、この発明の一実施例を図について説明
する。図1は本発明の側断面図で、同図において従来技
術と同一の符号を付したものは同一の構成を示すもので
あり、詳細な説明は省略する。本発明の特徴とするとこ
ろは、回路パターン2上および外部リード5上に金(A
u)あるいははんだ(Pb−Su)からなるバンプ9を
形成し、これら両バンプ9間を銅(Cu)箔等が表面に
存在する導電テープ11で接続し、全体をエポキシ等の
樹脂で封止した点にある。このような構成とすることに
より、外部リード5と回路パターン2とは、電気的特性
が良好であるバンプと銅箔の組合わせにより、接続され
るとともに、外部リード5は隣接するリード間の間隔を
さほど開けずにテープ11と接続することができる。ま
た、樹脂封止を行うことにより量産性にすぐれている。 なお、バンプ9の形成方法としては、予め導電テープ1
1の両端に形成しておいてもよいことは勿論である。
【0007】図2は本発明の第2の実施例を示すもので
あり、この第2の実施例では、基板1側にのみバンプ9
を形成して、このバンプ9と外部リード5との接続を銅
(Cu)、金(Au)あるいはアルミニウム(Al)等
の金属細線4によって行ったものである。すなわち、金
属細線4の一端をバンプ9に合金形成により接続すると
ともに、金属細線4の他端を外部リード5に圧接あるい
は圧着により接続したものである。このような構成とす
ることにより、上記した第1の実施例と同等の作用効果
ある。なお、接続状況に応じて、金属細線4を使用せず
に外部リード5を直接バンプ9に接続する方法としもよ
い。
【0008】
【発明の効果】以上のように、この発明によれば、基板
と外部リードをバンプと導電テープあるいは金属細線と
の組合わせにより接続するように構成したので、配線を
短縮でき、かつ高周波特性に優れる材料を使用できるの
で、半導体装置としての電気的特性が良好で、さらに複
合回路を小型ができる。また、全体を樹脂封止成形加工
をするため、量産性に優れ安価に製造できるとともに、
信頼性の高いものを得ることができる効果がある。
【図面の簡単な説明】
【図1】本発明の側断面図である。
【図2】本発明の第2の実施例の要部側面図である。
【図3】従来の全体斜視図である。
【図4】従来のコーティング加工を施した全体斜視図で
ある。
【図5】従来の側断面図である。
【図6】従来の第2の実施例の側断面図である。
【符号の説明】
1    絶縁基板 2    回路パターン 3    半導体素子 4    金属細線 5    外部リード 9    バンプ 10    封止樹脂 11    導電テープ

Claims (2)

    【特許請求の範囲】
  1. 【請求項1】  絶縁性材料からなり表面に回路パター
    ンが形成された基板と、この基板に搭載され前記回路パ
    ターンの一方の接続部と電気的に接続された電極を有す
    る複数の半導体素子と、前記回路パターンの他方の接続
    部と電気的に接続された外部リードとからなる複合回路
    型半導体装置において、前記回路パターンの他方の接続
    部および外部リードの接続部に金あるいははんだでバン
    プを形成し、これらバンプ間を銅箔を表面に有するテー
    プで接続し、全体を封止樹脂で成形加工したことを特徴
    とする複合回路型半導体装置。
  2. 【請求項2】  絶縁性材料からなり表面に回路パター
    ンが形成された基板と、この基板に搭載され前記回路パ
    ターンの一方の接続部と電気的に接続された電極を有す
    る複数の半導体素子と、前記回路パターンの他方の接続
    部と電気的に接続された外部リードとからなる複合回路
    型半導体装置において、前記回路パターンの他方の接続
    部に金あるいははんだでバンプを形成し、このバンプに
    銅、金あるいはアルミニウムからなる金属細線の一方を
    合金形成により接続するとともに、金属細線の他方を前
    記外部リードに圧接あるいは圧着により接続し、全体を
    封止樹脂で成形加工したことを特徴とする複合回路型半
    導体装置。
JP3141600A 1991-06-13 1991-06-13 複合回路型半導体装置 Pending JPH04365340A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3141600A JPH04365340A (ja) 1991-06-13 1991-06-13 複合回路型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3141600A JPH04365340A (ja) 1991-06-13 1991-06-13 複合回路型半導体装置

Publications (1)

Publication Number Publication Date
JPH04365340A true JPH04365340A (ja) 1992-12-17

Family

ID=15295784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3141600A Pending JPH04365340A (ja) 1991-06-13 1991-06-13 複合回路型半導体装置

Country Status (1)

Country Link
JP (1) JPH04365340A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100444174B1 (ko) * 2001-12-28 2004-08-11 동부전자 주식회사 리드온칩 패키지

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100444174B1 (ko) * 2001-12-28 2004-08-11 동부전자 주식회사 리드온칩 패키지

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