JPH04365340A - Composite circuit type semiconductor device - Google Patents

Composite circuit type semiconductor device

Info

Publication number
JPH04365340A
JPH04365340A JP3141600A JP14160091A JPH04365340A JP H04365340 A JPH04365340 A JP H04365340A JP 3141600 A JP3141600 A JP 3141600A JP 14160091 A JP14160091 A JP 14160091A JP H04365340 A JPH04365340 A JP H04365340A
Authority
JP
Japan
Prior art keywords
circuit pattern
semiconductor device
type semiconductor
bumps
connection part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3141600A
Other languages
Japanese (ja)
Inventor
Hideyuki Ichiyama
一山　秀之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3141600A priority Critical patent/JPH04365340A/en
Publication of JPH04365340A publication Critical patent/JPH04365340A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To decrease electric noise and quicken response speed and elevate reliability. CONSTITUTION:A circuit pattern 2 is made on an insulating board 1, and a semiconductor chip 3 is loaded through an adhesive 7. The electrode of the semiconductor chip and the circuit pattern 2 are connected by a metallic thin wire 4. Bumps 9 made of gold or solder are made on said circuit pattern 2 and an outer lead 5. And both these bumps 9 are connected by a conductive tape 11 which has a copper foil on the surface, and the whole is molded with sealing resin 10.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は、複合回路型半導体装置
の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a composite circuit type semiconductor device.

【０００２】0002

【従来の技術】図３は従来の複合回路型半導体装置の全
体斜視図であり、同図において、１はセラミック等の絶
縁性材料からなる絶縁基板、２はこの絶縁基板１の表面
に形成されている回路パターン、３は表面に集積回路が
形成され、裏面を接着剤７で回路パターン２上に固着さ
れている半導体素子、４はこの半導体素子３の電極と回
路パターン２を接続している金属細線、５は回路パター
ン２とはんだ等で接続されており、外部と電気信号のや
りとりを行う外部リードである。そして、基板１に搭載
された半導体素子３および接続線である金属細線４は、
これを保護する目的で、図４および図５に示すように、
ポッティング樹脂１６等により基板１上にコーティング
される。このコーティングは図４に示すように部分的に
行う場合もあり、また全体的に行う場合もある。また、
半導体素子３を基板１に搭載する方法としては、図６に
示すように、半導体素子３の集積回路が形成されている
面と、基板１の回路パターン２が形成されている面とを
向かい合わせ、半導体素子３上の電極８と回路パターン
２をバンプ９により接続する方法もある。2. Description of the Prior Art FIG. 3 is an overall perspective view of a conventional composite circuit type semiconductor device. 3 is a semiconductor element on which an integrated circuit is formed on the front surface and is fixed on the circuit pattern 2 with an adhesive 7 on the back side; 4 is a semiconductor element that connects the electrodes of this semiconductor element 3 and the circuit pattern 2; A thin metal wire 5 is connected to the circuit pattern 2 by solder or the like, and is an external lead for exchanging electrical signals with the outside. The semiconductor element 3 mounted on the substrate 1 and the thin metal wire 4 serving as a connection line are
To protect this, as shown in Figures 4 and 5,
The substrate 1 is coated with a potting resin 16 or the like. This coating may be done partially, as shown in FIG. 4, or entirely. Also,
As shown in FIG. 6, the method for mounting the semiconductor element 3 on the substrate 1 is to place the surface of the semiconductor element 3 on which the integrated circuit is formed and the surface on which the circuit pattern 2 of the substrate 1 is formed facing each other. Another method is to connect the electrode 8 on the semiconductor element 3 and the circuit pattern 2 using bumps 9.

【０００３】0003

【発明が解決しようとする課題】従来の複合回路型半導
体装置は以上のように構成されているので、基板上の一
部分あるいは全面的にポッティング樹脂等でコーティン
グしなければならず、液状の樹脂を滴下させるという工
程が必要で、生産性や製品となった後の信頼性に問題が
あった。また、外部リードは基板にはんだ付け等で接続
されているので、リード間に一定以上の間隔を確保しな
ければならず端子の数が増えると基板面積が大きくなっ
てしまう等の問題点があった。この発明は上記のような
問題点を解消するためになされたもので、複合回路型半
導体装置を小型化できるとともに、半導体素子から外部
リードまでの距離が非常に短縮され、かつ高周波特性の
よい銅箔等が使用可能とし、電気的ノイズが少なく、応
答速度も早く、さらに信頼性も高い複合回路型半導体装
置を得ることを目的とする。[Problems to be Solved by the Invention] Since the conventional composite circuit type semiconductor device is constructed as described above, it is necessary to coat a portion or the entire surface of the substrate with potting resin, etc. A dripping process was required, which caused problems with productivity and reliability after the product was manufactured. In addition, since the external leads are connected to the board by soldering, etc., a certain distance must be maintained between the leads, which poses problems such as increasing the number of terminals and increasing the board area. Ta. This invention was made in order to solve the above-mentioned problems. It not only makes it possible to miniaturize a composite circuit type semiconductor device, but also greatly shortens the distance from the semiconductor element to the external lead. It also uses copper, which has good high frequency characteristics. The object of the present invention is to obtain a composite circuit type semiconductor device which can use foil or the like, has little electrical noise, has a fast response speed, and has high reliability.

【０００４】0004

【課題を解決するための手段】この目的を達成するため
に、この発明に係る複合回路型半導体装置は、絶縁性材
料からなり表面に回路パターンが形成された基板と、こ
の基板に搭載され前記回路パターンの一方の接続部と電
気的に接続された電極を有する複数の半導体素子と、前
記回路パターンの他方の接続部と電気的に接続された外
部リードとからなり、前記回路パターンの他方の接続部
および外部リードの接続部に金あるいははんだでバンプ
を形成し、これらバンプ間を銅箔を表面に有するテープ
で接続し、全体を封止樹脂で成形加工したものである。 また、本発明に係る複合回路型半導体装置は、絶縁性材
料からなり表面に回路パターンが形成された基板と、こ
の基板に搭載され前記回路パターンの一方の接続部と電
気的に接続された電極を有する複数の半導体素子と、前
記回路パターンの他方の接続部と電気的に接続された外
部リードとからなり、前記回路パターンの他方の接続部
に金あるいははんだでバンプを形成し、このバンプに銅
、金あるいはアルミニウムからなる金属細線の一方を合
金形成により接続するとともに、金属細線の他方を前記
外部リードに圧接あるいは圧着により接続し、全体を封
止樹脂で成形加工したものである。[Means for Solving the Problems] In order to achieve this object, a composite circuit type semiconductor device according to the present invention includes a substrate made of an insulating material and having a circuit pattern formed on its surface, and a circuit pattern mounted on the substrate. It consists of a plurality of semiconductor elements having electrodes electrically connected to one connection part of the circuit pattern, and an external lead electrically connected to the other connection part of the circuit pattern, Bumps are formed with gold or solder at the connecting portions and the connecting portions of the external leads, these bumps are connected with tape having copper foil on the surface, and the whole is molded with sealing resin. Further, the composite circuit type semiconductor device according to the present invention includes a substrate made of an insulating material and having a circuit pattern formed on its surface, and an electrode mounted on the substrate and electrically connected to one connection part of the circuit pattern. and an external lead electrically connected to the other connection part of the circuit pattern, a bump is formed with gold or solder on the other connection part of the circuit pattern, and One of the thin metal wires made of copper, gold, or aluminum is connected by alloy formation, and the other thin metal wire is connected to the external lead by pressure contact or pressure bonding, and the whole is molded with a sealing resin.

【０００５】[0005]

【作用】この発明における外部リードと回路パターンと
の接続はバンプと銅箔の組合わせによるもであり、電気
的特性が良好である。また、この発明における外部リー
ドへの接続はテープあるいは金属細線によるものであり
、端子数の増加に対しても基板面積をさほど大きくする
必要がない。[Operation] The connection between the external lead and the circuit pattern in this invention is based on a combination of bumps and copper foil, and has good electrical characteristics. Further, in this invention, the connection to the external leads is made by tape or thin metal wire, so there is no need to increase the board area so much even when the number of terminals increases.

【０００６】[0006]

【実施例】以下、この発明の一実施例を図について説明
する。図１は本発明の側断面図で、同図において従来技
術と同一の符号を付したものは同一の構成を示すもので
あり、詳細な説明は省略する。本発明の特徴とするとこ
ろは、回路パターン２上および外部リード５上に金（Ａ
ｕ）あるいははんだ（Ｐｂ−Ｓｕ）からなるバンプ９を
形成し、これら両バンプ９間を銅（Ｃｕ）箔等が表面に
存在する導電テープ１１で接続し、全体をエポキシ等の
樹脂で封止した点にある。このような構成とすることに
より、外部リード５と回路パターン２とは、電気的特性
が良好であるバンプと銅箔の組合わせにより、接続され
るとともに、外部リード５は隣接するリード間の間隔を
さほど開けずにテープ１１と接続することができる。ま
た、樹脂封止を行うことにより量産性にすぐれている。 なお、バンプ９の形成方法としては、予め導電テープ１
１の両端に形成しておいてもよいことは勿論である。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a side cross-sectional view of the present invention. In the figure, the same reference numerals as in the prior art indicate the same configurations, and detailed description thereof will be omitted. The feature of the present invention is that gold (A
u) Form bumps 9 made of solder or solder (Pb-Su), connect these two bumps 9 with conductive tape 11 with copper (Cu) foil etc. on the surface, and seal the whole thing with resin such as epoxy. That's what I did. With this configuration, the external leads 5 and the circuit pattern 2 are connected by a combination of bumps and copper foil that have good electrical characteristics, and the external leads 5 are connected to each other by a distance between adjacent leads. It can be connected to the tape 11 without opening it much. Moreover, by performing resin sealing, mass productivity is excellent. Incidentally, as a method for forming the bumps 9, the conductive tape 1 is
Of course, they may be formed at both ends of 1.

【０００７】図２は本発明の第２の実施例を示すもので
あり、この第２の実施例では、基板１側にのみバンプ９
を形成して、このバンプ９と外部リード５との接続を銅
（Ｃｕ）、金（Ａｕ）あるいはアルミニウム（Ａｌ）等
の金属細線４によって行ったものである。すなわち、金
属細線４の一端をバンプ９に合金形成により接続すると
ともに、金属細線４の他端を外部リード５に圧接あるい
は圧着により接続したものである。このような構成とす
ることにより、上記した第１の実施例と同等の作用効果
ある。なお、接続状況に応じて、金属細線４を使用せず
に外部リード５を直接バンプ９に接続する方法としもよ
い。FIG. 2 shows a second embodiment of the present invention. In this second embodiment, bumps 9 are provided only on the substrate 1 side.
The bump 9 is connected to the external lead 5 using a thin metal wire 4 made of copper (Cu), gold (Au), aluminum (Al), or the like. That is, one end of the thin metal wire 4 is connected to the bump 9 by alloy formation, and the other end of the thin metal wire 4 is connected to the external lead 5 by pressure contact or compression bonding. With such a configuration, the same effect as the first embodiment described above can be obtained. Note that depending on the connection situation, a method may be adopted in which the external lead 5 is directly connected to the bump 9 without using the thin metal wire 4.

【０００８】[0008]

【発明の効果】以上のように、この発明によれば、基板
と外部リードをバンプと導電テープあるいは金属細線と
の組合わせにより接続するように構成したので、配線を
短縮でき、かつ高周波特性に優れる材料を使用できるの
で、半導体装置としての電気的特性が良好で、さらに複
合回路を小型ができる。また、全体を樹脂封止成形加工
をするため、量産性に優れ安価に製造できるとともに、
信頼性の高いものを得ることができる効果がある。[Effects of the Invention] As described above, according to the present invention, the circuit board and external leads are connected by a combination of bumps and conductive tape or thin metal wires, so wiring can be shortened and high frequency characteristics can be improved. Since superior materials can be used, the electrical characteristics of the semiconductor device are good, and the composite circuit can be made smaller. In addition, since the entire body is molded with resin, it is highly mass-producible and can be manufactured at low cost.
This has the effect of making it possible to obtain highly reliable products.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】本発明の側断面図である。FIG. 1 is a side sectional view of the present invention.

【図２】本発明の第２の実施例の要部側面図である。FIG. 2 is a side view of essential parts of a second embodiment of the present invention.

【図３】従来の全体斜視図である。FIG. 3 is an overall perspective view of a conventional device.

【図４】従来のコーティング加工を施した全体斜視図で
ある。FIG. 4 is an overall perspective view showing a conventional coating process.

【図５】従来の側断面図である。FIG. 5 is a side sectional view of a conventional device.

【図６】従来の第２の実施例の側断面図である。FIG. 6 is a side sectional view of a second conventional example.

【符号の説明】[Explanation of symbols]

１　　　　絶縁基板 ２　　　　回路パターン ３　　　　半導体素子 ４　　　　金属細線 ５　　　　外部リード ９　　　　バンプ １０　　　　封止樹脂 １１　　　　導電テープ 1 Insulating substrate 2 Circuit pattern 3 Semiconductor device 4 Thin metal wire 5 External lead 9 Bump 10 Sealing resin 11 Conductive tape

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】　　絶縁性材料からなり表面に回路パター
ンが形成された基板と、この基板に搭載され前記回路パ
ターンの一方の接続部と電気的に接続された電極を有す
る複数の半導体素子と、前記回路パターンの他方の接続
部と電気的に接続された外部リードとからなる複合回路
型半導体装置において、前記回路パターンの他方の接続
部および外部リードの接続部に金あるいははんだでバン
プを形成し、これらバンプ間を銅箔を表面に有するテー
プで接続し、全体を封止樹脂で成形加工したことを特徴
とする複合回路型半導体装置。1. A substrate made of an insulating material and having a circuit pattern formed on its surface; a plurality of semiconductor elements having electrodes mounted on the substrate and electrically connected to one connection portion of the circuit pattern; In a composite circuit type semiconductor device comprising an external lead electrically connected to the other connection part of the circuit pattern, bumps are formed with gold or solder at the other connection part of the circuit pattern and the connection part of the external lead. , a composite circuit type semiconductor device characterized in that these bumps are connected by a tape having a copper foil on the surface, and the whole is molded with a sealing resin. 【請求項２】　　絶縁性材料からなり表面に回路パター
ンが形成された基板と、この基板に搭載され前記回路パ
ターンの一方の接続部と電気的に接続された電極を有す
る複数の半導体素子と、前記回路パターンの他方の接続
部と電気的に接続された外部リードとからなる複合回路
型半導体装置において、前記回路パターンの他方の接続
部に金あるいははんだでバンプを形成し、このバンプに
銅、金あるいはアルミニウムからなる金属細線の一方を
合金形成により接続するとともに、金属細線の他方を前
記外部リードに圧接あるいは圧着により接続し、全体を
封止樹脂で成形加工したことを特徴とする複合回路型半
導体装置。2. A substrate made of an insulating material and having a circuit pattern formed on its surface; and a plurality of semiconductor elements having electrodes mounted on the substrate and electrically connected to one connection portion of the circuit pattern; In a composite circuit type semiconductor device comprising an external lead electrically connected to the other connection part of the circuit pattern, a bump is formed on the other connection part of the circuit pattern with gold or solder, and this bump is coated with copper, A composite circuit type characterized in that one of the thin metal wires made of gold or aluminum is connected by alloy formation, and the other thin metal wire is connected to the external lead by pressure welding or crimping, and the whole is molded with a sealing resin. Semiconductor equipment.
JP3141600A 1991-06-13 1991-06-13 Composite circuit type semiconductor device Pending JPH04365340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3141600A JPH04365340A (en) 1991-06-13 1991-06-13 Composite circuit type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3141600A JPH04365340A (en) 1991-06-13 1991-06-13 Composite circuit type semiconductor device

Publications (1)

Publication Number Publication Date
JPH04365340A true JPH04365340A (en) 1992-12-17

Family

ID=15295784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3141600A Pending JPH04365340A (en) 1991-06-13 1991-06-13 Composite circuit type semiconductor device

Country Status (1)

Country Link
JP (1) JPH04365340A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100444174B1 (en) * 2001-12-28 2004-08-11 동부전자 주식회사 lead on chip package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100444174B1 (en) * 2001-12-28 2004-08-11 동부전자 주식회사 lead on chip package

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