JPH04216655A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04216655A
JPH04216655A JP40302390A JP40302390A JPH04216655A JP H04216655 A JPH04216655 A JP H04216655A JP 40302390 A JP40302390 A JP 40302390A JP 40302390 A JP40302390 A JP 40302390A JP H04216655 A JPH04216655 A JP H04216655A
Authority
JP
Japan
Prior art keywords
semiconductor element
island
leads
peltier element
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP40302390A
Other languages
Japanese (ja)
Inventor
Naoto Kimura
直人 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP40302390A priority Critical patent/JPH04216655A/en
Publication of JPH04216655A publication Critical patent/JPH04216655A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce the temperature rise of a semiconductor element, and realize excellent operation, by mounting a Peltier element on the rear side of an island on which a semiconductor element is mounted, and connecting the Peltier element with leads by using wires. CONSTITUTION:A semiconductor element 3 is mounted on an island 4, and connected with leads 5 by using wires 2. A resin package 6 is formed by using resin. A Peltier element 1 also is mounted on the rear side of the island 4, and connected with the leads 5 by using wires 2p. Many leads 5 are prepared, and the semiconductor element 3 and the Peltier element 1 are connected with separate leads.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

【０００２】0002

【従来の技術】従来一般的な半導体装置は、図２に示す
様な縦断面図を有していた。つまり、半導体素子３はア
イランド４に搭載されボンディングワイヤ２によりリー
ド５へ接続され、樹脂パッケージ６にてバッケージンガ
されている。2. Description of the Related Art Conventionally, a common semiconductor device has a vertical cross-sectional view as shown in FIG. That is, the semiconductor element 3 is mounted on the island 4, connected to the leads 5 by the bonding wires 2, and packaged with the resin package 6.

【０００３】0003

【発明が解決しようとする課題】従来一般的な半導体装
置は、半導体素子を動作させた時の発熱にて半導体素子
の温度が上昇しても、樹脂パッケージ６を介しての冷却
では温度が下がらず半導体素子の動作不具合を招くとい
う問題点があった。[Problems to be Solved by the Invention] In conventional semiconductor devices, even if the temperature of the semiconductor element rises due to heat generation when the semiconductor element is operated, the temperature cannot be lowered by cooling through the resin package 6. However, there is a problem in that the semiconductor device may malfunction.

【０００４】0004

【課題を解決するための手段】本発明の半導体装置には
、半導体素子が搭載されたアイランドの裏側にペルチェ
素子が搭載され、かつワイヤ２にてリードへ接続されて
いる。半導体素子の動作時にペルチェ素子も動作する。[Means for Solving the Problems] In the semiconductor device of the present invention, a Peltier element is mounted on the back side of an island on which a semiconductor element is mounted, and is connected to a lead by a wire 2. When the semiconductor element operates, the Peltier element also operates.

【０００５】[0005]

【実施例】次に本発明について図面を参照して説明する
。図１は本発明の一実施例の半導体装置の縦断面図であ
る。半導休素子３はアイランド４に搭載されワイヤ２に
よりリード５へ接続され樹脂より成形され樹脂パッケー
ジ６となっている。ペルチェ素子１も同じくアイランド
４の裏側へ搭載されワイヤ２９によりリード５へ接続さ
れている。なおリード５は多数本用意されており、半導
体素子３とペルチェ素子１は別個のリードへ接続されて
いる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a longitudinal sectional view of a semiconductor device according to an embodiment of the present invention. A semiconducting idle element 3 is mounted on an island 4, connected to a lead 5 by a wire 2, and molded from resin to form a resin package 6. The Peltier element 1 is also mounted on the back side of the island 4 and connected to the lead 5 by a wire 29. Note that a large number of leads 5 are prepared, and the semiconductor element 3 and the Peltier element 1 are connected to separate leads.

【０００６】半導体素子３は動作時に発熱し温度上昇を
招くが、ある温度以上になると動作不具合を生じる。こ
の時ペルチェ素子１に別のリードとワイヤ２Ｐを通じて
電流を流して動作させると熱を吸収し放熱するために半
導体素子３の温度上昇を防止できる。[0006] The semiconductor element 3 generates heat during operation, leading to a rise in temperature, and when the temperature exceeds a certain level, malfunctions occur. At this time, when the Peltier element 1 is operated by passing a current through another lead and wire 2P, the temperature of the semiconductor element 3 can be prevented from rising because it absorbs and radiates heat.

【０００７】[0007]

【発明の効果】以上説明した様に、ペルチェ素子を半導
体素子を搭載したアイランドの裏側に搭載し、半導体素
子が動作する際ペルチェ素子も動作するために半導体素
子の動作による発熱がペルチェ素子により急速に冷却さ
れて、半導体素子の温度上昇を低下させ良好な動作を保
てるという効果がある。[Effects of the Invention] As explained above, the Peltier element is mounted on the back side of the island on which the semiconductor element is mounted, and when the semiconductor element operates, the Peltier element also operates, so the heat generated by the operation of the semiconductor element is rapidly generated by the Peltier element. This has the effect of reducing the temperature rise of the semiconductor element and maintaining good operation.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.

【図２】従来の半導体装置の一例の縦断面図である。FIG. 2 is a longitudinal cross-sectional view of an example of a conventional semiconductor device.

【符号の説明】 １　　　　ペルチェ素子 ２　　　　ワイヤ ３　　　　半導体素子 ４　　　　アイランド ５　　　　リード ６　　　　樹脂パッケージ[Explanation of symbols] 1 Peltier element 2 Wire 3 Semiconductor device 4 Island 5 Lead 6 Resin package

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　半導体素子が搭載されたアイランドの
裏側にペルチェ素子が搭載されていることを特徴とする
半導体装置。1. A semiconductor device characterized in that a Peltier element is mounted on the back side of an island on which a semiconductor element is mounted.
JP40302390A 1990-12-18 1990-12-18 Semiconductor device Pending JPH04216655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP40302390A JPH04216655A (en) 1990-12-18 1990-12-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP40302390A JPH04216655A (en) 1990-12-18 1990-12-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04216655A true JPH04216655A (en) 1992-08-06

Family

ID=18512772

Family Applications (1)

Application Number Title Priority Date Filing Date
JP40302390A Pending JPH04216655A (en) 1990-12-18 1990-12-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04216655A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996030942A1 (en) * 1995-03-29 1996-10-03 Olin Corporation Components for housing an integrated circuit device
US5578869A (en) * 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
US5895964A (en) * 1993-06-30 1999-04-20 Pioneer Electronic Corporation Thermoelectric cooling system
US5921087A (en) * 1997-04-22 1999-07-13 Intel Corporation Method and apparatus for cooling integrated circuits using a thermoelectric module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6084849A (en) * 1983-10-15 1985-05-14 Mitsubishi Electric Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6084849A (en) * 1983-10-15 1985-05-14 Mitsubishi Electric Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895964A (en) * 1993-06-30 1999-04-20 Pioneer Electronic Corporation Thermoelectric cooling system
US5578869A (en) * 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
WO1996030942A1 (en) * 1995-03-29 1996-10-03 Olin Corporation Components for housing an integrated circuit device
US5921087A (en) * 1997-04-22 1999-07-13 Intel Corporation Method and apparatus for cooling integrated circuits using a thermoelectric module

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Effective date: 19970114