JPS6084849A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6084849A JPS6084849A JP19273983A JP19273983A JPS6084849A JP S6084849 A JPS6084849 A JP S6084849A JP 19273983 A JP19273983 A JP 19273983A JP 19273983 A JP19273983 A JP 19273983A JP S6084849 A JPS6084849 A JP S6084849A
- Authority
- JP
- Japan
- Prior art keywords
- heat
- semiconductor
- chip
- plate
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/38—Cooling arrangements using the Peltier effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明ｒ」、放熱の良好な半導体咬ＩＪＴＬＶＬ関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor chip IJTLVL with good heat dissipation.
従来、半得体素子の動作時に発する熱の放散は、第１図
に示す方法で行なわｎていた。すなわち。Conventionally, heat generated during operation of a semiconductor device has been dissipated by the method shown in FIG. Namely.
第１図において、（１）は半導体チップであり、（２）
は半導体チップ（１）と引き出しリード（８）とＷｅ続
する内部リード線であり、（４）はパッケージを構成す
る樹脂である。半導体チップ（１）の接合部で七の動Ｉ
’ｌｌ’によＶ発生した熱は、王として側１１ｉ１ （
４）の表面から対流伝熱と輻射伝熱とにエフ放畝丁ゐ。In Figure 1, (1) is a semiconductor chip, (2)
is an internal lead wire that connects the semiconductor chip (1) and the lead-out lead (8), and (4) is a resin that constitutes the package. Seven movements I at the junction of the semiconductor chip (1)
The heat generated by 'll' is the side 11i1 (
4) Convection heat transfer and radiation heat transfer from the surface.
ま７ｊ、同時Ｖｔ、引き出しリード（８）を通して図示
しない配設基板への伝専伝熱に工ってｔ放熱さｉｔてい
る。At the same time, the heat is dissipated by means of heat transfer to the mounting board (not shown) through the lead Vt and lead (8).
しかしながら、半導体テップ（１）の接合部あたジの発
熱量かわず〃・であっても、工Ｃｖ果績度が大きくなる
と、半導体テップ（１）でのつも隔置が人きくなるので
、半畳体チップ（１）と側屈（４）の表面との１１１」
の熱姐抗を下け、また、佃鹿（４Ｊ ＱＪ表曲を沌ＩＬ
る生気の鮎を増加させ°ても、放熱か十分子ｃ達成ざＩ
Ｌず、半４体の特性が発熱にエリ劣化することがある。However, even if the amount of heat generated per joint of the semiconductor chip (1) is small, as the engineering Cv performance increases, the spacing of the semiconductor chip (1) becomes difficult, so 111 between the body tip (1) and the surface of the lateral bend (4)
He lowered the heat resistance of Tsukuda (4J QJ) and Chaos IL.
Even if you increase the vitality of sweetfish, you won't be able to achieve heat dissipation or ten children.
However, the characteristics of the halves may deteriorate due to heat generation.
この発明は、前ｄピφ悄に基ついてなさＩしたものであ
り、半導体チップの近ｆｆＪＴＬ電子冷沫装匝葡設けて
、半導体チップの発熱を効果的に放熱し、温度特性の安
定した半導体装置を提供することを目的とするものでお
る。This invention is based on the previous idea, and includes a ffJTL electronic cooling droplet in the vicinity of the semiconductor chip to effectively dissipate the heat generated by the semiconductor chip and create a semiconductor with stable temperature characteristics. The purpose is to provide equipment.
次に、この発明の一′実施ψＵについて図１を参照しな
からｄ発明する。Next, a first embodiment ψU of the present invention will be described with reference to FIG.
第２図に２いて、（５）にＮ型半導体であり、（６）ａ
Ｐ型半導体であり、いずｎも吸熱板（７）ＶＣ取り付け
らｎる。吸熱板（７）に、ＭＩＪ記Ｎ型半尋半導５）３
工びＰ型半導体（６）葡取り付けた血とに反対側の囲を
、半導体チップ（１）を搭載する鎖板（８Ｊの表面に接
触して、扉板（８）に取り付けらｎる。前ａＣＮ型半専
半導体）に、第１の′ｌ１４ｉ倹（９）を有する第１の
放熱板調にも接続さｎ、捷た、削配Ｐ型半寺体（句は、
第２の′電極Ｑη會准する第２の放熱板（−にも依絖さ
ｆＬる。削配の工うにして電子冷体装置が構成さｆＬ、
第１の′嘔健（転用２（１）’電極＋１１１．１ｉ１４
１の放熱板調の一部表面あ・工び第２の放熱板（Ｉ２１
の一部表ＩｎＩ會噸いて、−子冷体鉄匝に碩１１ｉｑ
Ｌ匍Ｖｔモールドさｎている。なお、第２図ＶＣおいて
、ＭＩ図におけるのと同一の査号を付したものは第１図
に２けるのとＩＯＪ様の愼龍を市する部材である。2 in Figure 2, (5) is an N-type semiconductor, and (6) a
It is a P-type semiconductor, and a heat absorbing plate (7) is attached to the VC. On the heat absorption plate (7), MIJ N type half fat semiconductor 5) 3
The P-type semiconductor (6) is attached to the door plate (8) by touching the surface of the chain plate (8J) on which the semiconductor chip (1) is mounted. The first aCN type half-dedicated semiconductor) is also connected to the first heat sink having the first 'l14i(9) n, twisted, and cut-out P type half-dedicated body (the phrase is,
The second heat dissipation plate (-) is also used to connect the second electrode Qη.
1st 'Kyoken (diversion 2 (1)' electrode + 111.1i14
The second heat sink (I21
Part of the table InI meeting, - 11iq in the cold body iron box
There is a L-shaped Vt mold. In addition, in Figure 2 VC, the parts with the same symbols as those in the MI diagram are those shown in Figure 1 at 2 and are the parts that connect IOJ's Shinryu.
半導体装置を、第２図に示すようＶＣ電子冷？ＪＩＬ装
置を組み込んで構成した場合、第２図に示す矢印方間に
′亀訛を通じると、通じる電流に比Ｖ１１シて吸熱板（
７ンが低温になる。そうすると、半導体チップ（υと吸
熱板（７ンとの間の温度勾配が大きくなり、半導体チッ
プ（１）からの伝熱量が増加し、半導体チップ（１）の
温度が低下することとなる。また、半導体チップ（１ン
で光生じた熱Ｍは、吸熱板（７へＮ型半専体（５］およ
びＰ型半寺体（６）を伝導して、第１の放熱板調と第２
の放熱板調とｙｃ集中する。その結果、第１の放熱板調
２工びか２の放熱板（Ｉ２１は、仙１ｊ飢句の表１１］
、ｃり尚温ＶＣなり、つまり第１の放熱板調お工び第２
の放熱板（１２１と夕本気との温度差が大きくなり、対
流伝熱お工ひ暢射伝熱が増加することＶＣより、半導体
装置全体からの放熱を十分な１％のとすることができる
。したがって、半導体テップ（υの動作中Ｖｔ過熱する
の全有効に防止することができ、半導体装置の温度特性
を一段と同上させることができる。Is the semiconductor device VC electronically cooled as shown in Figure 2? When a JIL device is installed in the configuration, if a curve is passed in the direction of the arrow shown in Fig. 2, the heat absorbing plate (
7n becomes low temperature. Then, the temperature gradient between the semiconductor chip (υ) and the heat absorption plate (7) increases, the amount of heat transferred from the semiconductor chip (1) increases, and the temperature of the semiconductor chip (1) decreases. , the heat M generated by the semiconductor chip (1) is conducted to the heat absorbing plate (7) through the N-type half-body (5) and the P-type half-body (6), and is transferred to the first heat sink and the second heat sink.
The heat sink tone and yc are concentrated. As a result, the first heat sink (I21 is Table 11 of Sen 1j Hikiku)
, C is a still temperature VC, that is, the first heat sink is similar to the second heat sink.
The temperature difference between the heat dissipation plate (121 and the heat sink) increases, and convection heat transfer increases radiant heat transfer.By VC, the heat dissipation from the entire semiconductor device can be reduced to a sufficient 1%. Therefore, overheating of Vt during operation of the semiconductor chip (υ) can be completely prevented, and the temperature characteristics of the semiconductor device can be further improved.
以上、この発明の一実施例について詳述したが、この発
明＃′；を前ａＣ冥施世’ＪＶＣ眠足さＩＬるものでは
なく、Ｃの発明の要旨の軛囲内で極々変形して実施する
ことができるのはいうまでＩ［１１ない。Although one embodiment of this invention has been described in detail above, this invention #' is not intended to be based on the previous aC 'JVC sleepy IL', but is carried out in a very modified manner within the scope of the gist of the invention of C. Needless to say, the only thing that can be done is I[11.
Ｍ’ｌＪ記央７１！ｉ例に半導体テップを冷却してその
発熱を外部に放散するものであるが、この発明に、ＬＳ
Ｉ、トランジスタ、サイリスク等の、動作により発熱を
伴なう能！ＩＩ］部品にも通用することができる。葦だ
、曲配実施例に、電子冷凍装置１段を組み込んだ半導体
装置であるが、より効率良〈冷却するために、を子冷凍
装置葡２段または七ｆＬ以上のｙ劫を血タリｖｃ黴枕し
、半纏体表直ＶＣ組み込んでもよい。M'lJKio71! An example of this invention is to cool a semiconductor chip and dissipate its heat to the outside.
Functions that generate heat due to operation, such as I, transistors, and Cyrisk! II] It can also be applied to parts. It is a semiconductor device that incorporates one stage of electronic refrigeration device in the arrangement example, but in order to achieve more efficient cooling, it is possible to use two stages of electronic refrigeration equipment or a y kalpa of more than 7 fL. It is also possible to incorporate a semi-integrated VC directly on the surface.
以上Ｖｔ詳述したようＶＣｌこの発明ＶＣよると、動作
することＶＣ工Ｖ兄熱する半寺悴テップ金直接に、効率
良く冷却するので、半導体チップの過熱を防止して、半
部′Ｉ４−装匝の温就峙注金一段と同上することができ
る。また１組み込んだ′電子冷凍装置にθ１ｔ、丁ｘｌ
Ａｃを調節すると、電子冷凍装置による冷却能力を任意
ＰＣすることができる。ま１ヒ、この発明の半導体装置
Ｖｔは、可動部分のない゛電子Ｃｖ凍装置を組み込んで
いるので、冷却に除し、騒音を発さす、また、摩耗もな
いので、寿命を半永久的なものとすることができる。As detailed above, VCl according to this invention VC operates by efficiently cooling the semiconductor chip directly to the heated metal, thereby preventing the semiconductor chip from overheating. It can be said to be the same as the 1st step of the pouring process. In addition, θ1t, dxl are installed in the electronic refrigeration system
By adjusting Ac, the cooling capacity of the electronic refrigeration system can be controlled arbitrarily. Also, since the semiconductor device Vt of the present invention incorporates an electronic CV freezing device that has no moving parts, it does not generate noise during cooling, and does not wear out, so its lifespan is semi-permanent. It can be done.
【図面の簡単な説明】
第１図は従来の半４悸装置を示す１ｌｆＴ曲図、および
、第２図はこの発明の一実施例である半導体装置を示す
断ｌｆ［］図である。
（１）：半導体テップ Ｌ５Ｊ ： Ｎ減半専拝（６）
：Ｐ型半導体 （７）：吸熱板
（８）二基板 調：第１の放熱板
（助：第２の放熱板
代理人 人 岩 瑠 雄BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a 1lfT diagram showing a conventional half-quadrupter device, and FIG. 2 is a cross-sectional lf[] diagram showing a semiconductor device as an embodiment of the present invention. (1): Semiconductor chip L5J: N reduction by half (6)
: P-type semiconductor (7): Heat absorbing plate (8) Two substrates Coordination: First heat sink (Assistant: Second heat sink agent) Ruo Iwa
Claims (1)
プを搭載する基板に配置する吸熱板と、前＝１吸熱板に
一端全接触するＮ型半尋体寂工びＰ型半導体と、前記Ｎ
型半導体の他端Ｖｔ接触して設けた第１の放熱板あ・工
び削配Ｐ型半尋体の他端にう安触して設けた第２の放熱
板とを儂え、Ｎ型半導体の他端から吸熱板を介してＰ型
半導体の他端へと′亀θＩＬを辿しることにエフ半導体
チックを冷却する電子冷凍装置金儲えたことを特徴とす
る半尋体装直。a semiconductor chip, a heat absorbing plate disposed in close proximity to the semiconductor chip on the substrate on which the semiconductor chip is mounted;
The first heat dissipation plate is placed in contact with the other end Vt of the type semiconductor, and the second heat dissipation plate is provided in contact with the other end of the machined P-type semicircular body. An electronic refrigeration device for cooling an F-semiconductor chip by tracing the ``torque θIL'' from the other end of the semiconductor to the other end of the P-type semiconductor via a heat absorbing plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19273983A JPS6084849A (en) | 1983-10-15 | 1983-10-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19273983A JPS6084849A (en) | 1983-10-15 | 1983-10-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6084849A true JPS6084849A (en) | 1985-05-14 |
Family
ID=16296253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19273983A Pending JPS6084849A (en) | 1983-10-15 | 1983-10-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6084849A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS625651U (en) * | 1985-06-25 | 1987-01-14 | ||
| JPH01245549A (en) * | 1988-03-26 | 1989-09-29 | Matsushita Electric Works Ltd | Semiconductor device and manufacture thereof |
| JPH04216655A (en) * | 1990-12-18 | 1992-08-06 | Nec Kyushu Ltd | Semiconductor device |
| JPH04320360A (en) * | 1991-03-23 | 1992-11-11 | Samsung Electron Co Ltd | Semiconductor package |
| US5224908A (en) * | 1989-11-15 | 1993-07-06 | Aisin Aw Co., Ltd. | Automatic transmission |
| US5537342A (en) * | 1990-08-28 | 1996-07-16 | Lsi Logic Corporation | Encapsulation of electronic components |
-
1983
- 1983-10-15 JP JP19273983A patent/JPS6084849A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS625651U (en) * | 1985-06-25 | 1987-01-14 | ||
| JPH01245549A (en) * | 1988-03-26 | 1989-09-29 | Matsushita Electric Works Ltd | Semiconductor device and manufacture thereof |
| US5224908A (en) * | 1989-11-15 | 1993-07-06 | Aisin Aw Co., Ltd. | Automatic transmission |
| US5537342A (en) * | 1990-08-28 | 1996-07-16 | Lsi Logic Corporation | Encapsulation of electronic components |
| JPH04216655A (en) * | 1990-12-18 | 1992-08-06 | Nec Kyushu Ltd | Semiconductor device |
| JPH04320360A (en) * | 1991-03-23 | 1992-11-11 | Samsung Electron Co Ltd | Semiconductor package |
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