JPH04246849A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04246849A JPH04246849A JP1173791A JP1173791A JPH04246849A JP H04246849 A JPH04246849 A JP H04246849A JP 1173791 A JP1173791 A JP 1173791A JP 1173791 A JP1173791 A JP 1173791A JP H04246849 A JPH04246849 A JP H04246849A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- island
- semiconductor device
- heat dissipating
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000011347 resin Substances 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 10
- 238000007789 sealing Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 abstract 2
- 238000000465 moulding Methods 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 4
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は半導体装置に関し、特に
樹脂封止型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device.
【0002】0002
【従来の技術】従来の半導体装置は、図2に示すように
半導体チップ4及びそれを固着したリードフレームのア
イランド3の全体を封止樹脂部1aで覆っている。2. Description of the Related Art In a conventional semiconductor device, as shown in FIG. 2, a semiconductor chip 4 and an island 3 of a lead frame to which it is fixed are entirely covered with a sealing resin portion 1a.
【0003】0003
【発明が解決しようとする課題】この従来の半導体装置
では、半導体チップの発熱に対して放熱性が悪く、特に
高消費電力の半導体チップが搭載できない欠点があった
。Problems to be Solved by the Invention This conventional semiconductor device has a drawback in that it has poor heat dissipation properties for the heat generated by the semiconductor chip, and in particular cannot mount a semiconductor chip with high power consumption.
【0004】0004
【課題を解決するための手段】本発明の半導体装置は、
アイランドの一主面に載置した半導体チップを封止する
樹脂部を有する半導体装置において、前記樹脂部が、前
記半導体チップ載置した領域に対応する前記アイランド
の他面を露出する凹部を有し、該凹部にはめこまれる凸
部を有する放熱板を装着して構成されている。[Means for Solving the Problems] A semiconductor device of the present invention includes:
In a semiconductor device having a resin part for sealing a semiconductor chip placed on one main surface of an island, the resin part has a recess exposing the other surface of the island corresponding to the area on which the semiconductor chip is placed. , a heat dissipation plate having a convex portion fitted into the concave portion is attached.
【0005】[0005]
【実施例】次に本発明について図面を参照して説明する
。図1は本発明の一実施例の半導体装置の断面図である
。半導体チップ4をアイランド3の片面に固着しワイヤ
ボンディングを終えたリードフレームのリード2の内部
を樹脂封止する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. A semiconductor chip 4 is fixed to one side of the island 3, and the inside of the leads 2 of the lead frame after wire bonding is sealed with resin.
【0006】この際、半導体チップ4を載置した方とは
反対側のリードフレームのアイランド3が露出するよう
考慮された凸形の金型を用いて樹脂封止する。その後に
放熱板7を露出したリードフレームのアイランド3に装
着する。At this time, resin sealing is performed using a convex mold designed to expose the island 3 of the lead frame on the side opposite to the side on which the semiconductor chip 4 is placed. After that, the heat sink 7 is attached to the exposed island 3 of the lead frame.
【0007】[0007]
【発明の効果】以上説明したように本発明は、半導体チ
ップを固着したリードフレームのアイランドに放熱板を
装着しているので、放熱性が高く従来よりも高消費電力
の半導体チップを搭載できるという効果を有する。[Effects of the Invention] As explained above, the present invention has a heat dissipation plate attached to the island of the lead frame to which the semiconductor chip is fixed, so it is possible to mount a semiconductor chip with high heat dissipation performance and higher power consumption than before. have an effect.
【図1】本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
【図2】従来の半導体装置の一例の断面図である。FIG. 2 is a cross-sectional view of an example of a conventional semiconductor device.
1 封止樹脂部 2 リード 3 アイランド 4 半導体チップ 5 ボンディングワイヤ 6 凹部 7 放熱板 1 Sealing resin part 2 Lead 3 Island 4 Semiconductor chip 5 Bonding wire 6 Recessed part 7 Heat sink
Claims (1)
チップを封止する樹脂部を有する半導体装置において、
前記樹脂部が、前記半導体チップ載置した領域に対応す
る前記アイランドの他面を露出する凹部を有し、該凹部
にはめこまれる凸部を有する放熱板を装着することを特
徴とする半導体装置。Claim 1. A semiconductor device having a resin part for sealing a semiconductor chip placed on one main surface of an island,
A semiconductor device characterized in that the resin part has a recess that exposes the other surface of the island corresponding to the area on which the semiconductor chip is mounted, and a heat sink having a projection fitted into the recess is attached. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1173791A JPH04246849A (en) | 1991-02-01 | 1991-02-01 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1173791A JPH04246849A (en) | 1991-02-01 | 1991-02-01 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04246849A true JPH04246849A (en) | 1992-09-02 |
Family
ID=11786345
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1173791A Pending JPH04246849A (en) | 1991-02-01 | 1991-02-01 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04246849A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2700416A1 (en) * | 1993-01-08 | 1994-07-13 | Mitsubishi Electric Corp | Semiconductor device having a semiconductor element on a mounting element. |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58100447A (en) * | 1981-12-11 | 1983-06-15 | Hitachi Ltd | Resin sealing type semiconductor device and manufacture thereof |
JPS6063952A (en) * | 1984-07-06 | 1985-04-12 | Hitachi Ltd | Mounting method for resin-sealed type semiconductor device |
-
1991
- 1991-02-01 JP JP1173791A patent/JPH04246849A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58100447A (en) * | 1981-12-11 | 1983-06-15 | Hitachi Ltd | Resin sealing type semiconductor device and manufacture thereof |
JPS6063952A (en) * | 1984-07-06 | 1985-04-12 | Hitachi Ltd | Mounting method for resin-sealed type semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2700416A1 (en) * | 1993-01-08 | 1994-07-13 | Mitsubishi Electric Corp | Semiconductor device having a semiconductor element on a mounting element. |
US5440169A (en) * | 1993-01-08 | 1995-08-08 | Mitsubishi Denki Kabushiki Kaisha | Resin-packaged semiconductor device with flow prevention dimples |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19970805 |