JPH08181268A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08181268A JPH08181268A JP32111694A JP32111694A JPH08181268A JP H08181268 A JPH08181268 A JP H08181268A JP 32111694 A JP32111694 A JP 32111694A JP 32111694 A JP32111694 A JP 32111694A JP H08181268 A JPH08181268 A JP H08181268A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor device
- circuit board
- heat sink
- resin package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置の放熱性の
向上を目的とする。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention aims at improving the heat dissipation of a semiconductor device.
【0002】[0002]
【従来の技術】従来のものとしては、半導体チップを封
止したパッケージの表面にヒートシンクを埋設したもの
がある。2. Description of the Related Art Conventionally, there is a package in which a heat sink is embedded in the surface of a package in which a semiconductor chip is sealed.
【0003】[0003]
【発明が解決しようとする課題】しかし、上記従来例で
は、樹脂パッケージの大きさに制限される等して、埋設
できるヒートシンクの放熱容量が制限されると言う欠点
を有していた。However, the above-mentioned conventional example has a drawback that the heat radiation capacity of the heat sink that can be embedded is limited due to the limitation of the size of the resin package.
【0004】本発明は、上記の点に鑑みてなされたもの
であり、充分な放熱容量の確保を容易にした半導体装置
を提供せんとするものである。The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device in which sufficient heat dissipation capacity can be easily secured.
【0005】[0005]
【課題を解決するための手段】請求項1記載のように、
半導体チップ6を搭載したダイパッド1を樹脂パッケー
ジ5で封止し、この樹脂パッケージ5からリード端子7
及びダイパッド1に連接した放熱フィン3を導出して成
ることを特徴とする半導体装置である。[Means for Solving the Problems] According to claim 1,
The die pad 1 on which the semiconductor chip 6 is mounted is sealed with a resin package 5, and the resin package 5 leads to the lead terminals 7
And a radiation fin 3 connected to the die pad 1 is led out.
【0006】ここで、放熱フィン3は、ダイパッド1の
下面側に切り起こして形成してもよいし、ダイパッド1
の端縁部に垂下連接して形成してもよい。Here, the heat radiation fins 3 may be formed by cutting and raising the lower surface side of the die pad 1.
It may be formed by being pendantly connected to the edge portion of.
【0007】また、放熱フィン3を回路基板2の表面ま
たは裏面に設けたヒートシンク8に接続してもよい。Further, the radiation fin 3 may be connected to a heat sink 8 provided on the front surface or the back surface of the circuit board 2.
【0008】[0008]
【作 用】この出願の発明によれば、樹脂パッケージ5
から導出した放熱フィン3に必要な容量のヒートシンク
8を接続できる。この結果、ダイパッド1に溜まる半導
体チップ6の熱を放熱フィン3を通じて効率よく放熱で
きる。[Operation] According to the invention of this application, the resin package 5
A heat sink 8 having a necessary capacity can be connected to the radiation fin 3 derived from the above. As a result, the heat of the semiconductor chip 6 accumulated in the die pad 1 can be efficiently radiated through the heat radiation fins 3.
【0009】この場合、ヒートシンク8を回路基板2に
設けると、放熱容量の設定が、樹脂パッケージ5の大き
さ等の制約を受けることなく、行える。とくに、ヒート
シンク8を回路基板2の回路を設けていない面に配置す
る場合にその自由度が高い。In this case, if the heat sink 8 is provided on the circuit board 2, the heat dissipation capacity can be set without being restricted by the size of the resin package 5 or the like. In particular, the degree of freedom is high when the heat sink 8 is arranged on the surface of the circuit board 2 on which the circuit is not provided.
【0010】[0010]
【実施例】以下、本発明を実施例に基づき説明する。EXAMPLES The present invention will be described below based on examples.
【0011】図1乃至図5に本発明の一実施例である半
導体装置を示す。この半導体装置は、半導体チップ6を
搭載したダイパッド1を樹脂パッケージ5で封止し、こ
の樹脂パッケージ5からリード端子7及びダイパッド1
に連接した放熱フィン3を導出して成るものである。1 to 5 show a semiconductor device which is an embodiment of the present invention. In this semiconductor device, a die pad 1 on which a semiconductor chip 6 is mounted is sealed with a resin package 5, and from this resin package 5, lead terminals 7 and die pad 1 are formed.
The heat radiation fin 3 connected to is derived.
【0012】放熱フィン3は、ダイパッド1の下面側
に、二列の、複数の切り起こしとして形成されている。The radiation fins 3 are formed on the lower surface side of the die pad 1 as a plurality of cut and raised portions in two rows.
【0013】リード端子7は、樹脂パッケージ5の両側
の側面から垂下されている。この半導体装置は、つぎの
ように使用される。The lead terminals 7 are hung from both side surfaces of the resin package 5. This semiconductor device is used as follows.
【0014】図4は、この一例を示し、この放熱フィン
3を回路基板2の表面に設けたヒートシンク8に半田付
け接続したものである。リード端子7も同様に、回路基
板2の表面に設れられた回路面に半田付け接続されてい
る。このような、実装構造は、一般に表面実装と言われ
ているものである。FIG. 4 shows an example of this, in which the radiation fin 3 is soldered and connected to a heat sink 8 provided on the surface of the circuit board 2. Similarly, the lead terminal 7 is also soldered and connected to the circuit surface provided on the surface of the circuit board 2. Such a mounting structure is generally called surface mounting.
【0015】図5は、他の使用例を示し、この放熱フィ
ン3を回路基板2に貫通すると共にこの裏面に設けたヒ
ートシンク8に半田付け接続したものである。リード端
子7は、回路基板2のスルホールに挿通したうえで、半
田付けされて、回路基板2の裏面に設けられた回路面と
接続されている。このような、実装構造は、一般にピン
実装と言われているものである。FIG. 5 shows another example of use in which the heat radiation fin 3 penetrates the circuit board 2 and is soldered to a heat sink 8 provided on the back surface thereof. The lead terminals 7 are inserted into the through holes of the circuit board 2 and then soldered to be connected to the circuit surface provided on the back surface of the circuit board 2. Such a mounting structure is generally called pin mounting.
【0016】図6乃至図10に本発明の異なる実施例で
ある半導体装置を示す。この半導体装置は、半導体チッ
プ6を搭載したダイパッド1を樹脂パッケージ5で封止
し、この樹脂パッケージ5からリード端子7及びダイパ
ッド1に連接した放熱フィン3を導出して成るものであ
る。6 to 10 show a semiconductor device which is a different embodiment of the present invention. In this semiconductor device, a die pad 1 on which a semiconductor chip 6 is mounted is sealed with a resin package 5, and a lead terminal 7 and a radiation fin 3 connected to the die pad 1 are led out from the resin package 5.
【0017】放熱フィン3はダイパッド1の端縁部に、
綴れ折り状にして連接垂下されている。The radiation fins 3 are provided on the edge of the die pad 1,
It is in the form of a folded fold and hangs down.
【0018】リード端子7は、樹脂パッケージ5の両側
の側面から垂下されている。この半導体装置は、つぎの
ように使用される。The lead terminals 7 are hung from both side surfaces of the resin package 5. This semiconductor device is used as follows.
【0019】図9は、この一の使用例を示し、この放熱
フィン3を回路基板2の表面に設けたヒートシンク8に
接続したものである。リード端子7も同様に、回路基板
2の表面に設れられた回路面に半田付け接続されてい
る。このような、実装構造は、一般に表面実装と言われ
ているものである。FIG. 9 shows one example of this use, in which this heat radiation fin 3 is connected to a heat sink 8 provided on the surface of the circuit board 2. Similarly, the lead terminal 7 is also soldered and connected to the circuit surface provided on the surface of the circuit board 2. Such a mounting structure is generally called surface mounting.
【0020】図10は、他の使用例を示し、この放熱フ
ィン3の下端部を回路基板2に貫通すると共にこの裏面
に設けたヒートシンク8に半田付け接続したものであ
る。リード端子7は、回路基板2のスルホールに挿通し
たうえで、半田付けされて、回路基板2の裏面に設けら
れた回路面と接続されている。この実装構造は、一般に
ピン実装と言われているものに類似するものである。FIG. 10 shows another example of use in which the lower end portion of the heat radiation fin 3 penetrates the circuit board 2 and is soldered to the heat sink 8 provided on the back surface thereof. The lead terminals 7 are inserted into the through holes of the circuit board 2 and then soldered to be connected to the circuit surface provided on the back surface of the circuit board 2. This mounting structure is similar to what is generally called pin mounting.
【0021】[0021]
【発明の効果】この出願の発明によれば、樹脂パッケー
ジ5から導出した放熱フィン3に必要な容量のヒートシ
ンク8を接続できる。この結果、ダイパッド1に溜まる
半導体チップ6の熱を放熱フィン3を通じて効率よく放
熱できる。According to the invention of this application, the heat sink 8 having a necessary capacity can be connected to the radiation fin 3 led out from the resin package 5. As a result, the heat of the semiconductor chip 6 accumulated in the die pad 1 can be efficiently radiated through the heat radiation fins 3.
【0022】この場合、ヒートシンク8を回路基板2に
設けると、放熱容量の設定が、樹脂パッケージ5の大き
さ等の制約を受けることなく、行える。とくに、ヒート
シンク8を回路基板2の回路を設けていない面に配置す
る場合にその自由度が高い。In this case, when the heat sink 8 is provided on the circuit board 2, the heat dissipation capacity can be set without being restricted by the size of the resin package 5 or the like. In particular, the degree of freedom is high when the heat sink 8 is arranged on the surface of the circuit board 2 on which the circuit is not provided.
【図 1】本発明の一実施例を示す断面図。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図 2】同上の斜視図。FIG. 2 is a perspective view of the same.
【図 3】同上の要部の斜視図。FIG. 3 is a perspective view of a main part of the above.
【図 4】同上の使用状態を示す断面図。FIG. 4 is a cross-sectional view showing a usage state of the same.
【図 5】同上の使用状態を示す断面図。FIG. 5 is a cross-sectional view showing a usage state of the same.
【図 6】本発明の異なる実施例を示す断面図。FIG. 6 is a sectional view showing another embodiment of the present invention.
【図 7】同上の斜視図。FIG. 7 is a perspective view of the above.
【図 8】同上の要部の斜視図。FIG. 8 is a perspective view of a main part of the above.
【図 9】同上の使用状態を示す断面図。FIG. 9 is a cross-sectional view showing a usage state of the same.
【図10】同上の使用状態を示す断面図。FIG. 10 is a cross-sectional view showing a usage state of the above.
1 ダイパッド 2 回路基板 3 放熱フィン 5 樹脂パッケージ 6 半導体チップ 7 リード端子 8 ヒートシンク 1 die pad 2 circuit board 3 radiating fins 5 resin package 6 semiconductor chip 7 lead terminal 8 heat sink
Claims (6)
を樹脂パッケージ5で封止し、この樹脂パッケージ5か
らリード端子7及びダイパッド1に連接した放熱フィン
3を導出して成ることを特徴とする半導体装置。1. A die pad 1 having a semiconductor chip 6 mounted thereon.
Is sealed with a resin package 5, and a radiation fin 3 connected to the lead terminal 7 and the die pad 1 is led out from the resin package 5.
熱フィン3を形成して成ることを特徴とする請求項1記
載の半導体装置。2. The semiconductor device according to claim 1, wherein the radiation pad 3 is formed by cutting and raising the die pad 1 on the lower surface side.
垂下連接して成ることを特徴とする請求項1記載の半導
体装置。3. The semiconductor device according to claim 1, wherein the radiation fins 3 are connected to the edge portions of the die pad 1 so as to hang down.
し、この放熱フィン3を回路基板2に設けたヒートシン
ク8に接続して成ることを特徴とする請求項1記載の半
導体装置。4. The semiconductor device according to claim 1, wherein the radiation fins 3 are hung and connected to the die pad 1, and the radiation fins 3 are connected to a heat sink 8 provided on the circuit board 2.
し、この放熱フィン3を回路基板2の表面に設けたヒー
トシンク8に接続して成ることを特徴とする半導体装
置。5. A semiconductor device, characterized in that a radiation fin (3) is hung and connected to a die pad (1) and the radiation fin (3) is connected to a heat sink (8) provided on the surface of a circuit board (2).
し、この放熱フィン3を回路基板2に貫通すると共にこ
の裏面に設けたヒートシンク8に接続して成ることを特
徴とする半導体装置。6. A semiconductor device, characterized in that a radiation fin 3 is hung and connected to a die pad 1, the radiation fin 3 penetrates the circuit board 2 and is connected to a heat sink 8 provided on the back surface thereof.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32111694A JPH08181268A (en) | 1994-12-26 | 1994-12-26 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32111694A JPH08181268A (en) | 1994-12-26 | 1994-12-26 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08181268A true JPH08181268A (en) | 1996-07-12 |
Family
ID=18129003
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32111694A Withdrawn JPH08181268A (en) | 1994-12-26 | 1994-12-26 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08181268A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998013867A1 (en) * | 1996-09-24 | 1998-04-02 | Siemens Aktiengesellschaft | Connecting frame for a microelectronic component, manufacturing process and microelectronic component encompassing same |
JP2003031750A (en) * | 2001-07-13 | 2003-01-31 | Matsushita Electric Ind Co Ltd | Lead frame and semiconductor device using it |
CN102403281A (en) * | 2011-10-11 | 2012-04-04 | 常熟市广大电器有限公司 | High-performance packaging structure of chip |
TWI469283B (en) * | 2009-08-31 | 2015-01-11 | Advanced Semiconductor Eng | Package structure and package process |
-
1994
- 1994-12-26 JP JP32111694A patent/JPH08181268A/en not_active Withdrawn
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998013867A1 (en) * | 1996-09-24 | 1998-04-02 | Siemens Aktiengesellschaft | Connecting frame for a microelectronic component, manufacturing process and microelectronic component encompassing same |
JP2003031750A (en) * | 2001-07-13 | 2003-01-31 | Matsushita Electric Ind Co Ltd | Lead frame and semiconductor device using it |
TWI469283B (en) * | 2009-08-31 | 2015-01-11 | Advanced Semiconductor Eng | Package structure and package process |
CN102403281A (en) * | 2011-10-11 | 2012-04-04 | 常熟市广大电器有限公司 | High-performance packaging structure of chip |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20020305 |