JP2606974B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JP2606974B2 JP2606974B2 JP3041435A JP4143591A JP2606974B2 JP 2606974 B2 JP2606974 B2 JP 2606974B2 JP 3041435 A JP3041435 A JP 3041435A JP 4143591 A JP4143591 A JP 4143591A JP 2606974 B2 JP2606974 B2 JP 2606974B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- frame
- integrated circuit
- semiconductor integrated
- output circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Die Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体集積回路装置に
関し、特に高負荷電流を制御する集積回路を搭載した半
導体チップとフレームとを接合するための構造の改良に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to an improvement in a structure for joining a frame and a semiconductor chip mounted with an integrated circuit for controlling a high load current.
【０００２】[0002]
【従来の技術】図３は従来の半導体集積回路装置の説明
図であり、該装置における半導体チップ上での回路パタ
ーンの配置を示している。図において、１は半導体チッ
プ、２は該チップ１上の側辺部に形成された出力回路、
３は出力回路２の配線を取り出すパッドである。また図
４は上記出力回路２の主要部分の構成を示しており、図
中２ａ，２ｂはそれぞれ出力回路２を構成するトランジ
スタ及びダイオードである。2. Description of the Related Art FIG. 3 is an explanatory view of a conventional semiconductor integrated circuit device, and shows an arrangement of circuit patterns on a semiconductor chip in the device. In the figure, 1 is a semiconductor chip, 2 is an output circuit formed on a side portion on the chip 1,
Reference numeral 3 denotes a pad from which the wiring of the output circuit 2 is taken out. FIG. 4 shows a configuration of a main part of the output circuit 2. In the drawing, reference numerals 2a and 2b denote transistors and diodes constituting the output circuit 2, respectively.
【０００３】図５は上記半導体集積回路の断面構造を示
す図であり、図中５はフレームで、該フレーム５上に半
導体チップ１が配置され、チップ１上のパッド３とフレ
ーム５のリード５ａとがワイヤ７により接続されてい
る。５４は上記フレーム５に半導体チップ１を固定する
ためのダイボンド剤、６は上記半導体チップ１及びフレ
ーム５を、該リード５ａの一部を除いて封止しているパ
ッケージである。また５２は半導体チップ１上の、出力
回路２を配置した部分である。FIG. 5 is a view showing a cross-sectional structure of the semiconductor integrated circuit. In FIG. 5, reference numeral 5 denotes a frame, on which a semiconductor chip 1 is arranged, and a pad 3 on the chip 1 and a lead 5a of the frame 5. Are connected by a wire 7. Reference numeral 54 denotes a die bonding agent for fixing the semiconductor chip 1 to the frame 5, and reference numeral 6 denotes a package that seals the semiconductor chip 1 and the frame 5 except for some of the leads 5a. Reference numeral 52 denotes a portion on the semiconductor chip 1 where the output circuit 2 is arranged.
【０００４】次に動作について説明する。上記半導体チ
ップ１上に形成された出力回路２は図４の出力トランジ
スタ２ａ群等により外部への電流供給を制御する。この
とき飽和電圧等による電力消費が起こり、ジュール熱が
生ずる。これらの熱はパッド３に接続されたワイヤ７か
らも放出されるが、大部分はダイボンド剤５４からフレ
ーム５に伝わりパッケージ６より空中へ放出される。Next, the operation will be described. The output circuit 2 formed on the semiconductor chip 1 controls external current supply by the output transistors 2a and the like in FIG. At this time, power consumption occurs due to a saturation voltage or the like, and Joule heat is generated. These heats are also released from the wires 7 connected to the pads 3, but most of the heat is transmitted from the die bonding agent 54 to the frame 5 and released from the package 6 to the air.
【０００５】[0005]
【発明が解決しようとする課題】ところが、従来の半導
体集積回路装置では、出力回路２は半導体チップ１の外
周近傍に分散して配置されているので、出力回路２で発
生した熱による温度上昇がチップ１全体に及ぶこととな
り、チップ１及びフレーム５の熱膨張はダイボンド部分
全面で起こる。またチップ１の材質がシリコン、フレー
ム５の材質が鉄系である場合には、熱抵抗の低い銅系の
フレームが大電流制御用半導体集積回路に多く使われる
が、この場合シリコンチップと銅系フレームの熱膨張率
の差は大きく、チップ割れが発生するなどの問題があっ
た。However, in the conventional semiconductor integrated circuit device, since the output circuits 2 are arranged in a distributed manner near the outer periphery of the semiconductor chip 1, the temperature rise due to the heat generated in the output circuits 2 occurs. The thermal expansion of the chip 1 and the frame 5 occurs over the entire die 1. If the chip 1 is made of silicon and the frame 5 is made of iron, a copper frame having a low thermal resistance is often used for a large current control semiconductor integrated circuit. The difference in the coefficient of thermal expansion of the frame was large, and there were problems such as chip cracking.
【０００６】この発明は上記のような問題点を解消する
ためになされたもので、発熱によるチップの割れを抑制
でき、信頼性の高い大電流制御の可能な半導体集積回路
を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor integrated circuit which can suppress chip breakage due to heat generation and can control a large current with high reliability. I do.
【０００７】[0007]
【課題を解決するための手段】本発明に係る半導体集積
回路は、出力回路等の発熱部を有する半導体チップにつ
いては、該チップ裏面の、出力回路等の配設部分と対応
する部分でのみフレームとダイボンド接合したものであ
る。In a semiconductor integrated circuit according to the present invention, a semiconductor chip having a heat generating portion such as an output circuit has a frame only at a portion corresponding to a portion where an output circuit and the like are provided on the back surface of the chip. And die-bonded.
【０００８】またこの発明は、上記半導体集積回路にお
いて、出力回路等の発熱部をチップ中央部分に集めて配
置し、チップ裏面中央部分でのみフレームとチップとを
ダイボンド接合したものである。Further, according to the present invention, in the above-mentioned semiconductor integrated circuit, heat generating portions such as an output circuit are gathered and arranged at a central portion of the chip, and the frame and the chip are die-bonded only at the central portion of the back surface of the chip.
【０００９】[0009]
【作用】この発明においては、出力回路等の発熱部を有
する半導体チップについては、該チップ裏面の、出力回
路等の配設部分と対応する部分でのみフレームとダイボ
ンド接合したから、出力回路等から発生する熱は、発熱
部裏面の接合部より集中的にフレームに伝わることとな
り、発熱による温度上昇がチップ全体に及ぶことはなく
なる。この結果チップとフレームとの間の熱応力による
チップの割れを抑制することができる。According to the present invention, a semiconductor chip having a heat generating portion such as an output circuit is die-bonded to a frame only on a portion corresponding to a portion where an output circuit and the like are provided on the back surface of the chip. The generated heat is intensively transmitted to the frame from the joint on the back surface of the heat generating portion, and the temperature rise due to the heat does not reach the entire chip. As a result, cracking of the chip due to thermal stress between the chip and the frame can be suppressed.
【００１０】[0010]
【実施例】図１及び図２は本発明の一実施例による半導
体集積回路を説明するための図であり、図１は半導体集
積回路内の半導体チップ上での回路パターンの配置を示
し、図２は上記半導体集積回路の断面構造を示してい
る。図において、図３及び図５と同一符号は同一のもの
を示し、１０は半導体チップで、ここでは、該チップ１
０の中央部に発熱部である出力回路２を集めて配置し、
該チップ裏面の、出力回路の配設部分と対応する部分で
のみフレームとダイボンド接合している。なお、２２は
半導体チップ上の出力回路２を配置した部分、２４はチ
ップ１０裏面の、出力回路２配置部分に対応する部分
と、フレーム５とを接合する部分ダイボンド剤で、例え
ば半田を用いている。1 and 2 are views for explaining a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 1 shows an arrangement of circuit patterns on a semiconductor chip in the semiconductor integrated circuit. Reference numeral 2 denotes a cross-sectional structure of the semiconductor integrated circuit. In the drawings, the same reference numerals as those in FIGS. 3 and 5 denote the same components, and reference numeral 10 denotes a semiconductor chip.
The output circuit 2 which is a heat generating part is collected and arranged at the center of 0,
Only the portion of the back surface of the chip corresponding to the portion where the output circuit is provided is die-bonded to the frame. Incidentally, the portion of arranging the output circuit 2 on the semiconductor chip 22, 24 is used and the portion corresponding to the chip 1 0 of the back, the output circuit 2 arranged portions, the portion die bonding agent for bonding the frame 5, for example, a solder ing.
【００１１】次に作用効果について説明する。上記半導
体チップ１０上に形成された出力回路２では、その動作
の際、ジュール熱が生ずるが、発熱部である出力回路２
はチップ中央部に集中して配置され、しかも半導体チッ
プ１０は該出力回路２の配置部分２２の裏面側でのみフ
レームと接合されているため、発生した熱は発熱部裏面
の部分ダイボンド剤２４を介して集中的にフレーム５に
伝わり、パッケージ６を介して放熱されることとなり、
発熱による温度上昇がチップ全体に及ぶことはなく、熱
膨張率の影響を受けにくくなる。また発熱部の下側はフ
レームとダイボンド剤を介して接触しているため、発生
した熱は効果的にフレームに放熱されることとなり、十
分な放熱効果が得られる。この結果銅系のフレームを用
いても、チップとフレームとの間の熱応力によるチップ
の割れを招くことなく、チップサイズを大きくとれる効
果がある。Next, the function and effect will be described. In the semiconductor chip 1 0 output circuit formed on the 2, during its operation, but Joule heat is generated, a heat generating portion output circuit 2
Chip is placed concentrated on the central portion, yet because it is joined to the frame only at the semiconductor chip 1 0 a rear surface of the placement portion 22 of the output circuit 2, the heat generated in the heat generating portion rear surface portion die bonding agent 24 is Through the package 6 and radiated through the package 6,
The temperature rise due to heat generation does not reach the entire chip, and is less affected by the coefficient of thermal expansion. Further, since the lower side of the heat generating portion is in contact with the frame via the die bonding agent, the generated heat is effectively radiated to the frame, and a sufficient heat radiation effect is obtained. As a result, even when a copper-based frame is used, there is an effect that the chip size can be increased without causing chip breakage due to thermal stress between the chip and the frame.
【００１２】なお上記実施例では、両側にフレームリー
ドのあるパッケージを示したが、これは片側にのみのフ
レームリードを有するパッケージであってもよい。In the above embodiment, a package having frame leads on both sides has been described. However, this may be a package having frame leads on only one side.
【００１３】また上記実施例では、出力回路をチップ中
央部に集めたが、出力回路はチップ一側方に偏寄らせて
配置してもよい。In the above embodiment, the output circuits are arranged in the central portion of the chip. However, the output circuits may be arranged so as to be shifted to one side of the chip.
【００１４】[0014]
【発明の効果】以上のようにこの発明によれば、出力回
路等の発熱部を有する半導体チップについては、該チッ
プ裏面の、発熱部である出力回路等の配設部分と対応す
る部分でのみフレームとダイボンド接合したので、発熱
部で発生した熱は発熱部裏面のダイボンド部から集中的
にフレームに伝わることとなり、このためチップとの熱
膨張率の差が大きい銅系のフレームを用いても、チップ
及びフレーム間の熱応力によるチップの割れを招くこと
なく、チップサイズを大きくとれる。これにより信頼性
の高い大電流制御の可能な半導体集積回路装置を得るこ
とができる。As described above, according to the present invention, with respect to a semiconductor chip having a heat generating portion such as an output circuit, only the portion corresponding to the portion where the output circuit or the like as the heat generating portion is provided on the back surface of the chip. Because of the die-bonding with the frame, the heat generated in the heat-generating part will be transferred to the frame from the die-bond part on the back of the heat-generating part. In addition, the chip size can be increased without causing chip breakage due to thermal stress between the chip and the frame. Thus, a highly reliable semiconductor integrated circuit device capable of controlling a large current can be obtained.
【図１】この発明の一実施例による半導体集積回路装置
に搭載したチップ上での回路パターンの配置を示す平面
図である。FIG. 1 is a plan view showing an arrangement of circuit patterns on a chip mounted on a semiconductor integrated circuit device according to one embodiment of the present invention.
【図２】上記チップの断面構造を示す図である。FIG. 2 is a diagram showing a sectional structure of the chip.
【図３】従来の半導体集積回路装置に搭載した半導体チ
ップ上での回路パターンの配置を示す平面図である。FIG. 3 is a plan view showing an arrangement of circuit patterns on a semiconductor chip mounted on a conventional semiconductor integrated circuit device.
【図４】該従来装置の半導体チップ上に形成した出力回
路の主要構成部を示す図である。FIG. 4 is a diagram showing main components of an output circuit formed on a semiconductor chip of the conventional device.
【図５】上記従来装置の半導体チップの断面構造を示す
図である。FIG. 5 is a diagram showing a cross-sectional structure of a semiconductor chip of the conventional device.
【符号の説明】１ 従来のチップ ２ 出力回路 ３ パッド ５ フレーム ６ パッケージ ７ ワイヤ １０ チップ ２２ 出力回路配置部分 ２４ ダイボンド剤[Description of Signs] 1 Conventional chip 2 Output circuit 3 Pad 5 Frame 6 Package 7 Wire 10 Chip 22 Output circuit arrangement part 24 Die bonding agent
Claims (2)
プを有する半導体集積回路装置において、発熱量の多い
回路を有する半導体チップは、該チップ裏面の、上記回
路の配設部分と対応する部分でのみフレームとダイボン
ド接合されていることを特徴とする半導体集積回路装
置。In a semiconductor integrated circuit device having a semiconductor chip die-bonded on a frame, the semiconductor chip having a circuit generating a large amount of heat is formed on the back surface of the chip only at a portion corresponding to a portion where the circuit is provided. A semiconductor integrated circuit device which is die-bonded.
チップ中央部分に集めて配置し、チップ裏面中央部分で
のみフレームとダイボンド接合したものであることを特
徴とする請求項１記載の半導体集積回路装置。2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor chip is formed by arranging a plurality of output circuits in a central portion of the chip and bonding the frame to the frame only in a central portion of the back surface of the chip. Circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3041435A JP2606974B2 (en) | 1991-01-24 | 1991-01-24 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3041435A JP2606974B2 (en) | 1991-01-24 | 1991-01-24 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04240737A JPH04240737A (en) | 1992-08-28 |
| JP2606974B2 true JP2606974B2 (en) | 1997-05-07 |
Family
ID=12608295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3041435A Expired - Lifetime JP2606974B2 (en) | 1991-01-24 | 1991-01-24 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2606974B2 (en) |
-
1991
- 1991-01-24 JP JP3041435A patent/JP2606974B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04240737A (en) | 1992-08-28 |
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