JP2691312B2 - Package for storing semiconductor elements - Google Patents
Package for storing semiconductor elementsInfo
- Publication number
- JP2691312B2 JP2691312B2 JP1312727A JP31272789A JP2691312B2 JP 2691312 B2 JP2691312 B2 JP 2691312B2 JP 1312727 A JP1312727 A JP 1312727A JP 31272789 A JP31272789 A JP 31272789A JP 2691312 B2 JP2691312 B2 JP 2691312B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lid
- external lead
- lead terminal
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体素子を収容する半導体素子収納用パッ
ケージの改良に関するものである。Description: TECHNICAL FIELD The present invention relates to an improvement in a semiconductor device housing package for housing a semiconductor device.
（従来の技術） 従来、半導体素子を収容するためのパッケージ、特に
ガラスの溶着によって封止するガラス封止型半導体素子
収納用パッケージは、絶縁基体と蓋体とから成り、内部
に半導体素子を収容する空所を有する絶縁容器と、該容
器内に収容される半導体素子を外部電気回路に電気的に
接続するための外部リード端子とから構成されており、
絶縁基体及び蓋体の相対向する主面に予め封止用のガラ
ス部材を被着形成すると共に、絶縁基体主面に外部リー
ド端子を固定し、半導体素子の各電極と外部リード端子
とをワイヤボンド接続した後、絶縁基体及び蓋体のそれ
ぞに被着させた封止用のガラス部材を溶融一体化させる
ことによって内部に半導体素子を気密に封止している。(Prior Art) Conventionally, a package for accommodating a semiconductor element, particularly a package for accommodating a glass-encapsulated semiconductor element sealed by welding glass, includes an insulating base and a lid, and accommodates the semiconductor element inside. And an external lead terminal for electrically connecting a semiconductor element housed in the container to an external electric circuit,
A glass member for sealing is applied in advance on the opposing main surfaces of the insulating base and the lid, and external lead terminals are fixed on the main surface of the insulating base, and each electrode of the semiconductor element and the external lead terminal are wired. After the bond connection, the semiconductor element is hermetically sealed inside by fusing and integrating a sealing glass member attached to each of the insulating base and the lid.
（発明が解決しようとする課題） しかし乍ら、この従来のガラス封止型半導体素子収納
用パッケージは通常、外部リード端子がコバール（29wt
％ Ni-16wt％ Co-55wt％ Fe合金）や42Alloy（42wt
％ Ni-58wt％ Fe合金）の導電性材料から成ってお
り、該コバールや42Alloy等は導電率が低いことから以
下に述べる欠点を有する。(Problems to be Solved by the Invention) However, in the conventional glass-encapsulated semiconductor element housing package, the external lead terminal is usually a kovar (29 wt.
% Ni-16wt% Co-55wt% Fe alloy) or 42Alloy (42wt
% Ni-58 wt% Fe alloy), and Kovar, 42 Alloy, etc. have the following drawbacks because of their low electrical conductivity.
即ち、 コバールや42Alloyはその導電率が3.0〜3.5％（IAC
S）と低い。そのためこのコバールや42Alloy等から成る
外部リード端子に信号を伝搬させた場合、信号の伝搬速
度が極めて遅いものとなり、高速駆動を行う半導体素子
はその収容が不可となってしまう、 半導体素子収納用パッケージの内部に収容する半導
体素子の高密度化、高集積化の進展に伴い、半導体素子
の電極数が大幅に増大しており、半導体素子の各電極を
外部電気回路に接続する外部リード端子の線幅も極めて
細くなってきている。そのため外部リード端子は上記
に記載のコバールや42Alloyの導電率が低いことと相俊
って電気抵抗が極めて大きなものになってきており、外
部リード端子に信号を伝搬させると、該外部リード端子
の電気抵抗に起因して信号が大きく減衰し、内部に収容
する半導体素子に信号を正確に入力することができず、
半導体素子に誤動作を生じさせてしまう、 等の欠点を有していた。That is, Kovar and 42Alloy have a conductivity of 3.0 to 3.5% (IAC
S) and low. Therefore, when a signal is propagated to an external lead terminal made of Kovar or 42Alloy, the signal propagation speed becomes extremely slow, and semiconductor devices that perform high-speed driving cannot be accommodated. The number of electrodes of a semiconductor element has increased significantly with the progress of higher density and higher integration of semiconductor elements housed inside the semiconductor device, and wires of external lead terminals for connecting each electrode of the semiconductor element to an external electric circuit. The width has also become extremely narrow. Therefore, the external lead terminal has become extremely large in electrical resistance in conjunction with the low conductivity of Kovar and 42Alloy described above, and when a signal is propagated to the external lead terminal, the external lead terminal The signal is greatly attenuated due to the electric resistance, and the signal cannot be accurately input to the semiconductor element housed inside,
It has the drawback of causing malfunctions in semiconductor devices.
（発明の目的） 本発明は上記欠点に鑑み案出されたもので、その目的
は外部リード端子における信号の減衰を極小となし、内
部に収容する半導体素子への信号の入出力を確実に行う
ことを可能として半導体素子を長期間にわたり正常、且
つ安定に作動させることができる半導体素子収納用パッ
ケージを提供することにある。(Object of the Invention) The present invention has been devised in view of the above-mentioned drawbacks, and an object of the present invention is to minimize signal attenuation at an external lead terminal and to reliably input and output a signal to a semiconductor element housed therein. It is therefore an object of the present invention to provide a semiconductor element storage package that enables the semiconductor element to operate normally and stably for a long period of time.
また本発明の他の目的は高速駆動を行う半導体素子を
収容することができる半導体素子収納用パッケージを提
供することにある。Another object of the present invention is to provide a semiconductor element housing package capable of housing a semiconductor element which operates at high speed.
（課題を解決するための手段） 本発明は絶縁基体と蓋体とから成り、内部に半導体素
子を収容するための空所を有する絶縁容器と、該容器内
に収容される半導体素子を外部電気回路に接続するため
の外部リード端子とから成る半導体素子収納用パッケー
ジにおいて、前記絶縁基体及び蓋体を炭化珪素室焼結体
で、外部リード端子をインバー合金から成る板状体の上
下面に、該板状体の厚みに対し10乃至20％の厚みの銅板
を接合させた金属体で形成したことを特徴とするもので
ある。(Means for Solving the Problem) The present invention comprises an insulating container having an insulating base and a lid, and having a void space for housing a semiconductor element therein, and a semiconductor element housed in the container being electrically connected to an external electrical device. In a package for housing a semiconductor element, which comprises an external lead terminal for connecting to a circuit, the insulating substrate and the lid are made of a silicon carbide chamber sintered body, and the external lead terminal is provided on the upper and lower surfaces of a plate-shaped body made of an Invar alloy. It is characterized in that it is formed of a metal body in which a copper plate having a thickness of 10 to 20% of the thickness of the plate-like body is joined.
（実施例） 次に本発明を添付図面に基づき詳細に説明する。(Example) Next, the present invention will be described in detail with reference to the accompanying drawings.
第１図及び第２図は本発明の半導体素子収納用パッケ
ージの一実施例を示し、１は絶縁基体、２は蓋体であ
る。この絶縁基体１と蓋体２とにより絶縁容器３が構成
される。1 and 2 show an embodiment of a package for accommodating a semiconductor element according to the present invention, wherein 1 is an insulating base and 2 is a lid. The insulating container 3 is constituted by the insulating base 1 and the lid 2.
前記絶縁基体１及び蓋体２はそれぞれの中央部に半導
体素子を収容する空所を形成するための凹部が設けてあ
り、絶縁基体１の凹部底面には半導体素子４が樹脂、ガ
ラス、ロウ剤等の接着剤を介し取着固定される。The insulating base 1 and the lid 2 are each provided with a concave portion for forming a space for accommodating a semiconductor element at the center thereof, and the semiconductor element 4 is formed of resin, glass, brazing agent on the bottom surface of the concave portion of the insulating base 1. It is attached and fixed via an adhesive such as.
前記絶縁基体１及び蓋体２は炭化珪素質焼結体から成
り、第１図に示すような絶縁基体１及び蓋体２に対応し
た形状を有するプレス型内に、炭化珪素（SiC）、ベリ
リア（BeO）等の原料粉末を充填させ、しかる後、これ
に一定圧力を印加しながら約2000〜2200℃の温度で焼成
することによって製作される。The insulating base 1 and the lid 2 are made of a silicon carbide sintered body, and silicon carbide (SiC) and beryllia are placed in a press die having a shape corresponding to the insulating base 1 and the lid 2 as shown in FIG. It is manufactured by filling a raw material powder such as (BeO) and then firing it at a temperature of about 2000 to 2200 ° C. while applying a constant pressure thereto.
尚、前記絶縁基体１及び蓋体２を形成する炭化珪素質
焼結体はその熱膨張係数が約37×10-7／℃であり、後述
する封止用ガラス部材の熱膨張係数との関係において絶
縁基体１及び蓋体２と封止用ガラス部材間に大きな熱膨
張の差が生じることはない。The thermal expansion coefficient of the silicon carbide sintered body forming the insulating base 1 and the lid 2 is about 37 × 10 −7 / ° C., and the relationship with the thermal expansion coefficient of the sealing glass member described later. In, there is no large difference in thermal expansion between the insulating substrate 1 and the lid body 2 and the sealing glass member.
また前記絶縁基体１及び蓋体２にはその相対向する主
面に封止用のガラス部材６が予め被着形成されており、
該絶縁基体１及び蓋体２の各々に被着されている封止用
ガラス部材６を加熱溶融させ一体化させることにより絶
縁容器３内の半導体素子４を気密に封止する。Further, a glass member 6 for sealing is previously formed on the opposing main surfaces of the insulating base 1 and the lid 2.
The semiconductor element 4 in the insulating container 3 is hermetically sealed by heating and melting the sealing glass member 6 attached to each of the insulating base 1 and the lid 2 to be integrated.
前記絶縁基体１及び蓋体２の相対向する主面に被着さ
れる封止用ガラス部材６は、例えばホウケイ酸鉛系ガラ
スにフィラーを添加したものから成り、原料粉末として
の酸化鉛（PbO）70.0〜90.0wt％、酸化ホウ素（B2O3）1
2.0〜13.0wt％、シリカ（SiO2）0.5〜3.0wt％及びアル
ミナ（Al2O3）0.5〜3.0wt％にフィラーとしてチタン酸
鉛（PbTiO3）、β−ユークリプタイト（Li2Al2Si
2O8）、コージライト（Mg2Al4Si5O18）、ジルコン（ZrS
iO4）、酸化スズ（SnO2）、ウレイマイト（Zn2SiO4）等
を30〜50vol％添加混合すると共に、該混合粉末を950〜
1100℃の温度で加熱溶融させることによって製作され
る。このホウケイ酸鉛系のガラスはその熱膨張係数が40
〜60×10-7／℃である。The sealing glass member 6 adhered to the opposing main surfaces of the insulating substrate 1 and the lid 2 is made of, for example, lead borosilicate glass to which a filler is added, and lead oxide (PbO) as a raw material powder is used. ) 70.0-90.0wt%, boron oxide (B 2 O 3 ) 1
2.0 to 13.0 wt%, silica (SiO 2 ) 0.5 to 3.0 wt% and alumina (Al 2 O 3 ) 0.5 to 3.0 wt% lead titanate (PbTiO 3 ) as a filler, β-eucryptite (Li 2 Al 2 Si
2 O 8 ), cordierite (Mg 2 Al 4 Si 5 O 18 ), zircon (ZrS
iO 4 ), tin oxide (SnO 2 ), uremite (Zn 2 SiO 4 ) and the like are added and mixed in an amount of 30 to 50 vol%, and the mixed powder is added to 950 to
It is manufactured by heating and melting at a temperature of 1100 ° C. This lead borosilicate glass has a coefficient of thermal expansion of 40
It is ~ 60 x 10 -7 / ° C.
前記封止用ガラス部材６はその熱膨張係数が40〜60×
10-7／℃であり、絶縁基体１及び蓋体２の各々の熱膨張
係数と近似することから絶縁基体１及び蓋体２の各々に
被着されている封止用ガラス部材６を加熱溶融させ一体
化させることにより絶縁容器３内の半導体素子４を気密
に封止する際、絶縁基体１及び蓋体２と封止用ガラス部
材６との間には両者の熱膨張係数の相違に起因する熱応
力が発生することは殆どなく、絶縁基体１と蓋体２とを
封止用ガラス部材６を介し強固に接合することが可能と
なる。The sealing glass member 6 has a thermal expansion coefficient of 40 to 60 ×.
10 −7 / ° C., which is close to the thermal expansion coefficient of each of the insulating base 1 and the lid 2, so that the sealing glass member 6 attached to each of the insulating base 1 and the lid 2 is heated and melted. When the semiconductor element 4 in the insulating container 3 is hermetically sealed by being integrated with each other, due to the difference in thermal expansion coefficient between the insulating substrate 1 and the lid 2 and the sealing glass member 6. Almost no thermal stress is generated, and the insulating base body 1 and the lid body 2 can be firmly bonded to each other through the sealing glass member 6.
尚、前記封止用ガラス部材６はフィラーを添加したホ
ウケイ酸鉛系ガラスの粉末に適当な有機溶剤、溶媒を添
加して得たガラスペーストを従来周知の厚膜手法を採用
することによって絶縁基体１及び蓋体２の相対向する主
面に被着形成される。The sealing glass member 6 is made of a glass paste obtained by adding a suitable organic solvent and a solvent to a powder of lead borosilicate glass to which a filler has been added by employing a conventionally well-known thick film method. 1 and the cover 2 are attached to the opposing main surfaces.
また前記封止用ガラス部材６はフィラーを添加したホ
ウケイ酸鉛系のガラスに限定されるものではなく、熱膨
張係数が40〜60×10-7／℃の範囲のガラスであればいか
なるものでも使用することができる。The sealing glass member 6 is not limited to lead borosilicate glass to which a filler is added, and any glass having a coefficient of thermal expansion of 40 to 60 × 10 −7 / ° C. can be used. Can be used.
前記絶縁基体１と蓋体２との間には導電性材料から成
る外部リード端子５が配されており、該外部リード端子
５は半導体素子４の各電極がワイヤ７を介し電気的に接
続され、外部リード端子５を外部電気回路に接続するこ
とによって半導体素子４が外部電気回路に接続されるこ
ととなる。An external lead terminal 5 made of a conductive material is disposed between the insulating base 1 and the lid 2. The external lead terminal 5 is electrically connected to each electrode of the semiconductor element 4 via a wire 7. By connecting the external lead terminal 5 to an external electric circuit, the semiconductor element 4 is connected to the external electric circuit.
前記外部リード端子５は絶縁基体１と蓋体２の相対向
する主面に被着させた封止用ガラス部材６を溶融一体化
させ、絶縁容器３を気密封止する際に同時に絶縁基体１
と蓋体２との間に取着される。The external lead terminals 5 are formed by melting and integrating a sealing glass member 6 attached to the opposing main surfaces of the insulating base 1 and the lid 2, and simultaneously sealing the insulating container 3 with the insulating base 1.
And the cover 2.
前記外部リード端子５はインバー合金から成る板状体
の上下面に、該板状体の厚みに対し10乃至20％の厚みの
銅板を接合させた金属体から成り、その導電率は21.7％
（IACS）、熱膨張係数は約40×10-7／℃である。The external lead terminals 5 are made of a metal body in which a copper plate having a thickness of 10 to 20% of the thickness of the plate-like body is joined to the upper and lower surfaces of the plate-like body made of Invar alloy, and the conductivity thereof is 21.7%.
(IACS), coefficient of thermal expansion is about 40 × 10 -7 / ° C.
尚、前記外部リード端子５はインバー合金（36.5wt％
Ni-63.5wt％ Fe合金）から成る板状体の上下面に銅
（Cu）板を圧接し、しかる後、これを圧延することによ
って形成される。The external lead terminal 5 is made of Invar alloy (36.5 wt%
It is formed by press-contacting copper (Cu) plates on the upper and lower surfaces of a plate-shaped body made of Ni-63.5 wt% Fe alloy), and then rolling this.
また前記外部リード端子５は板状体と銅板の厚みが上
述の範囲を外れると外部リード端子５は導電率が所望の
大きな値にならず、また熱膨張係数も絶縁基体及び蓋体
の熱膨張係数と合わなくなる。そのため外部リード端子
５はインバー合金から成る板状体の上下面に、該板状体
の厚みに対し10乃至20％の厚みの銅板を接合させた金属
体で形成したものに限定される。If the thicknesses of the plate-shaped body and the copper plate of the external lead terminal 5 deviate from the above-mentioned ranges, the electrical conductivity of the external lead terminal 5 does not reach a desired large value, and the thermal expansion coefficient of the insulating base body and the lid body is also increased. It does not match the coefficient. Therefore, the external lead terminals 5 are limited to those formed of a metal body in which a copper plate having a thickness of 10 to 20% of the thickness of the plate-like body is joined to the upper and lower surfaces of the plate-like body made of Invar alloy.
前記外部リード端子５はその導電率が21.7％（IACS）
であり、電気を流し易いことから外部リード端子５の信
号伝搬速度を極めて速いものとなすことができ、絶縁容
器３内に収容した半導体素子４を高速駆動させたとして
も半導体素子４と外部電気回路との間における信号の出
し入れは常に安定、且つ確実になすことができる。The external lead terminal 5 has a conductivity of 21.7% (IACS).
Since the electric current can easily flow, the signal propagation speed of the external lead terminal 5 can be made extremely fast, and even if the semiconductor element 4 housed in the insulating container 3 is driven at high speed, The input and output of signals to and from the circuit can always be stable and reliable.
また外部リード端子５の導電率が高いことから外部リ
ード端子５の線幅が細くなったとしても外部リード端子
５の電気抵抗を低く抑えることができ、その結果、外部
リード端子５における信号の減衰を極小として内部に収
容する半導体素子４に外部電気回路から供給される電気
信号を正確に入力することができる。Further, since the electrical conductivity of the external lead terminal 5 is high, the electrical resistance of the external lead terminal 5 can be kept low even if the line width of the external lead terminal 5 is reduced, and as a result, signal attenuation at the external lead terminal 5 is achieved. The electric signal supplied from the external electric circuit can be accurately input to the semiconductor element 4 housed therein with the minimum value.
更に前記外部リード端子５はその熱膨張係数が約40×
10-7／℃であり、封止用ガラス部材６の熱膨張係数と近
似することから外部リード端子５を絶縁基体１と蓋体２
の間に封止用ガラス部材６を用いて固定する際、外部リ
ード端子５と封止用ガラス部材６との間には両者の熱膨
張係数の相違に起因する熱応力が発生することはなく、
外部リード端子５を封止用ガラス部材６で強固に固定す
ることも可能となる。Further, the coefficient of thermal expansion of the external lead terminal 5 is about 40 ×.
Since it is 10 −7 / ° C., which is close to the thermal expansion coefficient of the sealing glass member 6, the external lead terminal 5 is connected to the insulating base 1 and the lid 2.
When fixing using the sealing glass member 6 between them, no thermal stress is generated between the external lead terminal 5 and the sealing glass member 6 due to the difference in the coefficient of thermal expansion between them. ,
The external lead terminal 5 can also be firmly fixed by the sealing glass member 6.
かくして、この半導体素子収納用パッケージによれば
絶縁基体１の凹部底面に半導体素子４を取着固定すると
ともに該半導体素子４の各電極をボンディングワイヤ７
により外部リード端子５に接続させ、しかる後、絶縁基
体１と蓋体２とを該絶縁基体１及び蓋体２の相対向する
主面に予め被着させておいた封止用ガラス部材６を溶融
一体化させることによって接合させ、これによって最終
製品としての半導体装置が完成する。Thus, according to the package for accommodating the semiconductor element, the semiconductor element 4 is attached and fixed to the bottom surface of the concave portion of the insulating base 1 and each electrode of the semiconductor element 4 is connected to the bonding wire 7.
After that, the sealing glass member 6 in which the insulating substrate 1 and the lid 2 are previously adhered to the opposing main surfaces of the insulating substrate 1 and the lid 2 is removed. The semiconductor device as a final product is completed by joining by melting and integrating.
（発明の効果） 本発明の半導体素子収納用パッケージによれば、半導
体素子を収容するための絶縁容器を構成する絶縁基体及
び蓋体を炭化珪素質焼結体で、外部リード端子をインバ
ー合金から成る板状体の上下面に、該板状体の厚みに対
し10乃至20％の厚みの銅板を接合させた導電率が21.7％
（IACS）、熱膨張係数が約40×10-7／℃の金属体で形成
したことから外部リード端子の信号伝搬速度を極めて速
いものとなすことができ、絶縁容器内に収容した半導体
素子を高速駆動させたとしても半導体素子と外部電気回
路との間における信号の出し入れを常に安定、且つ確実
になすことが可能となる。(Effects of the Invention) According to the package for accommodating a semiconductor element of the present invention, the insulating substrate and the lid constituting the insulating container for accommodating the semiconductor element are made of a silicon carbide sintered body, and the external lead terminals are made of an Invar alloy. A copper plate having a thickness of 10 to 20% is bonded to the upper and lower surfaces of a plate-shaped body made of a conductive material having a conductivity of 21.7%.
(IACS), the coefficient of thermal expansion is about 40 × 10 -7 / ° C. Because it is made of a metal body, the signal propagation speed of the external lead terminal can be extremely fast, and the semiconductor element housed in the insulating container can be Even when driven at high speed, it is possible to always stably and surely input and output signals between the semiconductor element and the external electric circuit.
また外部リード端子の線幅が細くなったとしても外部
リード端子の電気抵抗を低く抑えることができ、その結
果、外部リード端子における信号の減衰を極小として内
部に収容する半導体素子に外部電気回路から供給される
電気信号を正確に入力することが可能となる。Also, even if the line width of the external lead terminal is reduced, the electric resistance of the external lead terminal can be kept low. The supplied electric signal can be input accurately.
更に外部リード端子はその熱膨張係数が絶縁基体、蓋
体及び封止用ガラス部材の各々の熱膨張係数と近似し、
絶縁基体と蓋体との間に外部リード端子を挟み、各々を
封止用ガラス部材で取着接合したとしても絶縁基体及び
蓋体と封止用ガラス部材との間、外部リード端子と封止
用ガラス部材との間のいずれにも熱膨張係数の相違に起
因する熱応力は発生せず、すべてを強固に取着接合する
ことも可能となる。Further, the thermal expansion coefficient of the external lead terminal is close to the thermal expansion coefficient of each of the insulating base, the lid and the sealing glass member,
Even when the external lead terminals are sandwiched between the insulating base and the lid, and each of them is attached and bonded by the sealing glass member, the external lead terminals and the sealing are provided between the insulating base and the lid and the sealing glass member. No thermal stress due to the difference in the coefficient of thermal expansion is generated between the glass member and the glass member, and it is possible to firmly attach and bond all of them.
第１図は本発明の半導体素子収納用パッケージの一実施
例を示す断面図、第２図は第１図に示すパッケージの絶
縁基体上面より見た平面図である。 １……絶縁基体、２……蓋体 ３……絶縁容器 ５……外部リード端子 ６……封止用ガラス部材FIG. 1 is a cross-sectional view showing one embodiment of a package for housing a semiconductor element according to the present invention, and FIG. 2 is a plan view of the package shown in FIG. DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Lid 3 ... Insulating container 5 ... External lead terminal 6 ... Glass member for sealing
Claims (1)
素子を収容するための空所を有する絶縁容器と、該容器
内に収容される半導体素子を外部電気回路に接続するた
めの外部リード端子とから成る半導体素子収納用パッケ
ージにおいて、前記絶縁基体及び蓋体を炭化珪素質焼結
体で、外部リード端子をインバー合金から成る板状体の
上下面に、該板状体の厚みに対し10乃至20％の厚みの銅
板を接合させた金属体で形成したことを特徴とする半導
体素子収納用パッケージ。1. An insulating container comprising an insulating base and a lid, and having a space for housing a semiconductor element therein, and an external container for connecting the semiconductor element housed in the container to an external electric circuit. In a package for accommodating a semiconductor element comprising lead terminals, the insulating substrate and the lid are made of a silicon carbide sintered body, and the external lead terminals are provided on the upper and lower surfaces of a plate-shaped body made of an Invar alloy and have a thickness of the plate-shaped body. A package for housing a semiconductor element, which is formed of a metal body in which copper plates having a thickness of 10 to 20% are joined.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1312727A JP2691312B2 (en) | 1989-11-30 | 1989-11-30 | Package for storing semiconductor elements |
| US07/574,472 US5168126A (en) | 1989-08-25 | 1990-08-27 | Container package for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1312727A JP2691312B2 (en) | 1989-11-30 | 1989-11-30 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03173159A JPH03173159A (en) | 1991-07-26 |
| JP2691312B2 true JP2691312B2 (en) | 1997-12-17 |
Family
ID=18032699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1312727A Expired - Fee Related JP2691312B2 (en) | 1989-08-25 | 1989-11-30 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2691312B2 (en) |
-
1989
- 1989-11-30 JP JP1312727A patent/JP2691312B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03173159A (en) | 1991-07-26 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |