JP7466482B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7466482B2 JP7466482B2 JP2021042533A JP2021042533A JP7466482B2 JP 7466482 B2 JP7466482 B2 JP 7466482B2 JP 2021042533 A JP2021042533 A JP 2021042533A JP 2021042533 A JP2021042533 A JP 2021042533A JP 7466482 B2 JP7466482 B2 JP 7466482B2
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- 239000004065 semiconductor Substances 0.000 title claims description 71
- 239000010410 layer Substances 0.000 claims description 132
- 239000000758 substrate Substances 0.000 claims description 43
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 41
- 229910052698 phosphorus Inorganic materials 0.000 claims description 41
- 239000011574 phosphorus Substances 0.000 claims description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 41
- 229920005591 polysilicon Polymers 0.000 claims description 41
- 238000009825 accumulation Methods 0.000 claims description 26
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 10
- 239000002344 surface layer Substances 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005204 segregation Methods 0.000 description 2
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Description
図1は、実施の形態1に係る半導体装置100の平面図である。図2は、当該半導体装置100の断面図であり、図2は、図1のA-A線に沿った断面を示している。本実施の形態では、半導体装置100の素子構造としてIGBTを示す。ただし、本開示に係る技術の適用はIGBTに限られず、MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor)やRC-IGBT(Reverse-Conducting IGBT)などのパワーデバイスに広く適用可能である。
実施の形態2に係る半導体装置100の構成は基本的に図1および図2と同様である。ただし、実施の形態2では、埋込電極11cにリンを含まない材料を用いる。そのような埋込電極11cの材料としては、例えば、ノンドープポリシリコン、窒素が添加されたドープドポリシリコン、金属などが挙げられる。埋込電極11cの材料としてリンが添加されたドープドポリシリコンを用いる実施の形態1と比較すると、ノンドープポリシリコンを用いる場合は、埋込電極11cの電気抵抗が高くなるが、窒素が添加されたドープドポリシリコンや金属を用いる場合は、埋込電極11cの電気抵抗を低減できる。
図3は、実施の形態3に係る半導体装置100の断面図であり、図2と同様に、図1のA-A線に沿った断面を示している。
実施の形態4に係る半導体装置100の構成は基本的に図1および図2と同様である。ただし、実施の形態4では、ゲートトレンチ電極11aにリンを含まない材料を用いる(当然、実施の形態1とは異なり、埋込電極11cに含まれるリンの濃度は、ゲートトレンチ電極11aに含まれるリンの濃度よりも高くてよい)。そのようなゲートトレンチ電極11aの材料としては、例えば、ノンドープポリシリコン、窒素が添加されたドープドポリシリコン、金属などが挙げられる。ゲートトレンチ電極11aの材料としてリンが添加されたドープドポリシリコンを用いる実施の形態1と比較すると、ノンドープポリシリコンを用いる場合は、ゲートトレンチ電極11aの電気抵抗が高くなるが、窒素が添加されたドープドポリシリコンや金属を用いる場合は、ゲートトレンチ電極11aの電気抵抗を低減できる。
図4は、実施の形態5に係る半導体装置100の断面図であり、図2と同様に、図1のA-A線に沿った断面を示している。
実施の形態6では、実施の形態1~5に係る半導体装置100の製造方法を説明する。図5は、その製造方法を示すフローチャートである。
Claims (5)
- 第1主面、第2主面および第1導電型のドリフト層を有する半導体基板と、
前記半導体基板において前記ドリフト層よりも前記第1主面側に形成され、前記ドリフト層よりも不純物のピーク濃度が高い前記第1導電型のキャリア蓄積層と、
前記半導体基板において前記キャリア蓄積層よりも前記第1主面側に形成された第2導電型のベース層と、
前記半導体基板において前記第1主面に接するように形成された、前記第1導電型のエミッタ層および前記第2導電型のコンタクト層と、
前記エミッタ層、前記ベース層および前記キャリア蓄積層に接して前記ドリフト層に達するトレンチ内に形成されたアクティブトレンチゲートと、
を備え、
前記アクティブトレンチゲートは、
前記トレンチの内壁に形成されたゲートトレンチ絶縁膜と、
前記トレンチ内において前記ゲートトレンチ絶縁膜上に形成され、互いに絶縁された、ゲートトレンチ電極および前記ゲートトレンチ電極よりも前記第2主面側に配設された埋込電極と、
を備え、
前記ゲートトレンチ電極および前記埋込電極の両方がリンを含んでおり、
前記埋込電極のリン濃度は、前記ゲートトレンチ電極のリン濃度より低い、
半導体装置。 - 第1主面、第2主面および第1導電型のドリフト層を有する半導体基板と、
前記半導体基板において前記ドリフト層よりも前記第1主面側に形成され、前記ドリフト層よりも不純物のピーク濃度が高い前記第1導電型のキャリア蓄積層と、
前記半導体基板において前記キャリア蓄積層よりも前記第1主面側に形成された第2導電型のベース層と、
前記半導体基板において前記第1主面に接するように形成された、前記第1導電型のエミッタ層および前記第2導電型のコンタクト層と、
前記エミッタ層、前記ベース層および前記キャリア蓄積層に接して前記ドリフト層に達するトレンチ内に形成されたアクティブトレンチゲートと、
を備え、
前記アクティブトレンチゲートは、
前記トレンチの内壁に形成されたゲートトレンチ絶縁膜と、
前記トレンチ内において前記ゲートトレンチ絶縁膜上に形成され、互いに絶縁された、ゲートトレンチ電極および前記ゲートトレンチ電極よりも前記第2主面側に配設された埋込電極と、
を備え、
前記埋込電極のリン濃度は、前記ゲートトレンチ電極のリン濃度より低く、
前記埋込電極は、リンを含まないノンドープポリシリコンで形成されている、
半導体装置。 - 第1主面、第2主面および第1導電型のドリフト層を有する半導体基板と、
前記半導体基板において前記ドリフト層よりも前記第1主面側に形成され、前記ドリフト層よりも不純物のピーク濃度が高い前記第1導電型のキャリア蓄積層と、
前記半導体基板において前記キャリア蓄積層よりも前記第1主面側に形成された第2導電型のベース層と、
前記半導体基板において前記第1主面に接するように形成された、前記第1導電型のエミッタ層および前記第2導電型のコンタクト層と、
前記エミッタ層、前記ベース層および前記キャリア蓄積層に接して前記ドリフト層に達するトレンチ内に形成されたアクティブトレンチゲートと、
を備え、
前記アクティブトレンチゲートは、
前記トレンチの内壁に形成されたゲートトレンチ絶縁膜と、
前記トレンチ内において前記ゲートトレンチ絶縁膜上に形成され、互いに絶縁された、ゲートトレンチ電極および前記ゲートトレンチ電極よりも前記第2主面側に配設された埋込電極と、
を備え、
前記埋込電極のリン濃度は、前記ゲートトレンチ電極のリン濃度より低く、
前記埋込電極は、窒素が添加されリンを含まないドープドポリシリコンで形成されている、
半導体装置。 - 第1主面、第2主面および第1導電型のドリフト層を有する半導体基板と、
前記半導体基板において前記ドリフト層よりも前記第1主面側に形成され、前記ドリフト層よりも不純物のピーク濃度が高い前記第1導電型のキャリア蓄積層と、
前記半導体基板において前記キャリア蓄積層よりも前記第1主面側に形成された第2導電型のベース層と、
前記半導体基板において前記第1主面に接するように形成された、前記第1導電型のエミッタ層および前記第2導電型のコンタクト層と、
前記エミッタ層、前記ベース層および前記キャリア蓄積層に接して前記ドリフト層に達するトレンチ内に形成されたアクティブトレンチゲートと、
を備え、
前記アクティブトレンチゲートは、
前記トレンチの内壁に形成されたゲートトレンチ絶縁膜と、
前記トレンチ内において前記ゲートトレンチ絶縁膜上に形成され、互いに絶縁された、ゲートトレンチ電極および前記ゲートトレンチ電極よりも前記第2主面側に配設された埋込電極と、
を備え、
前記埋込電極の表層部はノンドープポリシリコンで形成されており、前記埋込電極の前記表層部よりも内側はリンが添加されたドープドポリシリコンで形成されている、
半導体装置。 - 第1主面、第2主面および第1導電型のドリフト層を有する半導体基板と、
前記半導体基板において前記ドリフト層よりも前記第1主面側に形成され、前記ドリフト層よりも不純物のピーク濃度が高い前記第1導電型のキャリア蓄積層と、
前記半導体基板において前記キャリア蓄積層よりも前記第1主面側に形成された第2導電型のベース層と、
前記半導体基板において前記第1主面に接するように形成された、前記第1導電型のエミッタ層および前記第2導電型のコンタクト層と、
前記エミッタ層、前記ベース層および前記キャリア蓄積層に接して前記ドリフト層に達するトレンチ内に形成されたアクティブトレンチゲートと、
を備え、
前記アクティブトレンチゲートは、
前記トレンチの内壁に形成されたゲートトレンチ絶縁膜と、
前記トレンチ内において前記ゲートトレンチ絶縁膜上に形成され、互いに絶縁された、ゲートトレンチ電極および前記ゲートトレンチ電極よりも前記第2主面側に配設された埋込電極と、
を備え、
前記ゲートトレンチ電極の少なくとも表層部はリンを含んでおらず、
前記ゲートトレンチ電極の前記表層部はノンドープポリシリコンで形成されており、前記ゲートトレンチ電極の前記表層部よりも内側はリンが添加されたドープドポリシリコンで形成されている、
半導体装置。
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JP2013065774A (ja) | 2011-09-20 | 2013-04-11 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2014216444A (ja) | 2013-04-25 | 2014-11-17 | 三菱電機株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP2017147431A (ja) | 2016-02-12 | 2017-08-24 | 富士電機株式会社 | 半導体装置 |
JP2019012813A (ja) | 2017-06-29 | 2019-01-24 | 株式会社東芝 | 絶縁ゲート型バイポーラトランジスタ |
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