JP7282329B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 61
- 230000000630 rising effect Effects 0.000 claims description 15
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000008878 coupling Effects 0.000 description 12
- 238000010168 coupling process Methods 0.000 description 12
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- 239000000463 material Substances 0.000 description 7
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- 239000000758 substrate Substances 0.000 description 5
- 230000002123 temporal effect Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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Description
図1は、本発明の第一実施形態に係る半導体装置100の構成を、模式的に示す斜視図である。半導体装置100は、主に、ベース基板101と、ベース基板101上に積層された複数の半導体チップ102と、複数の半導体チップ102を積層方向Lに貫通し、一端がベース基板101に固定された貫通電極(TSV)103と、で構成されている。複数の半導体チップ102は、貫通電極103を介して電気的に接続されている。
図5は、本発明の第二実施形態に係る半導体装置200を、最上層の半導体チップ102側から見た平面図である。半導体装置200は、四種類の入出力信号を発生させることを想定し、四つの入出力素子104A、104B、104C、104Dを備えている。その他の構成については、第一実施形態の半導体装置100の構成と同様であり、半導体装置100と対応する箇所については、形状の違いによらず、同じ符号で示している。
101・・・ベース基板
102・・・半導体チップ
103、103A、103B、103C、103D・・・貫通電極
104、104A、104B、104C、104D・・・入出力素子
D1、D2、D3、D4・・・配置方向
L・・・積層方向
Claims (8)
- 積層された複数の半導体チップを、積層方向に貫通する複数の貫通電極を介して電気的に接続してなる半導体装置であって、
前記半導体チップ同士がバンプを介さずに接合され、
複数の前記貫通電極のそれぞれに接続された機能素子が、所定のタイミングでオンまたはオフの動作を行うように、複数の前記貫通電極のそれぞれに対し、信号の入出力動作を行う複数の入出力素子のいずれかが接続されており、
隣接する二つの前記貫通電極のうち、片方が接続された前記入出力素子と、他の片方が接続された前記入出力素子とが、互いに異なるタイミングで前記信号の入出力動作を行うように構成され、
前記片方が接続された前記入出力素子は、前記半導体チップの一端側に配置され、前記他の片方が接続された前記入出力素子は、前記半導体チップの他端側に配置されることを特徴とする半導体装置。 - 複数の前記入出力素子がクロック信号を発生させる外部電源に接続されており、
隣接する二つの前記貫通電極のうち、片方が接続された前記入出力素子が、発生した前記クロック信号の立ち上がりのタイミングで入出力動作を行うように構成され、
隣接する二つの前記貫通電極のうち、他の片方が接続された前記入出力素子が、発生した前記クロック信号の立ち下がりのタイミングで入出力動作を行うように構成されていることを特徴とする請求項1に記載の半導体装置。 - 複数の前記入出力素子がクロック信号を発生させる外部電源に接続されており、
隣接する二つの前記貫通電極のうち、片方が接続された前記入出力素子が、発生した前記クロック信号の奇数周期における立ち上がりまたは立ち下がりのタイミングで入出力動作を行うように構成され、
隣接する二つの前記貫通電極のうち、他の片方が接続された前記入出力素子が、発生した前記クロック信号の偶数周期における立ち上がりまたは立下がりのタイミングで入出力動作を行うように構成されていることを特徴とする請求項1に記載の半導体装置。 - 複数の前記入出力素子がクロック信号を発生させる外部電源に接続されており、
一方向において隣接する前記貫通電極が接続されるそれぞれの入出力素子と、他方向において隣接する前記貫通電極が接続されるそれぞれの入出力素子とが、互いに異なるタイミングで前記信号の入出力動作を行うように構成されていることを特徴とする請求項1に記載の半導体装置。 - 前記一方向において隣接する二つの前記貫通電極のうち、一方が接続された前記入出力素子が、発生した前記クロック信号の奇数周期における立ち上がりのタイミングで入出力動作を行うように構成され、
前記一方向において隣接する二つの前記貫通電極のうち、他方が接続された前記入出力素子が、発生した前記クロック信号の奇数周期における立ち下がりのタイミングで入出力動作を行うように構成され、
前記他方向において隣接する二つの前記貫通電極のうち、一方が接続された前記入出力素子が、発生した前記クロック信号の偶数周期における立ち上がりのタイミングで入出力動作を行うように構成され、
前記他方向において隣接する二つの前記貫通電極のうち、他方が接続された前記入出力素子が、発生した前記クロック信号の偶数周期における立ち下がりのタイミングで入出力動作を行うように構成されていることを特徴とする請求項4に記載の半導体装置。 - 複数の前記貫通電極がチェッカーパターンを形成するように配置されていることを特徴とする請求項1~5のいずれか一項に記載の半導体装置。
- 複数の前記貫通電極が千鳥格子パターンを形成するように配置されていることを特徴とする請求項1~5のいずれか一項に記載の半導体装置。
- 複数の前記貫通電極がハニカムパターンを形成するように配置されていることを特徴とする請求項1~5のいずれか一項に記載の半導体装置。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4252485B2 (ja) | 2004-03-29 | 2009-04-08 | 富士通マイクロエレクトロニクス株式会社 | スイッチングレギュレータ制御回路、スイッチングレギュレータ、およびスイッチングレギュレータ制御方法 |
JP2012243251A (ja) | 2011-05-24 | 2012-12-10 | Elpida Memory Inc | メモリシステム |
US20180374779A1 (en) | 2017-06-21 | 2018-12-27 | SK Hynix Inc. | Semiconductor device |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04252485A (ja) * | 1991-01-28 | 1992-09-08 | Hitachi Ltd | 半導体記憶装置 |
JP4309368B2 (ja) * | 2005-03-30 | 2009-08-05 | エルピーダメモリ株式会社 | 半導体記憶装置 |
JP5471439B2 (ja) * | 2007-03-09 | 2014-04-16 | 日本電気株式会社 | 半導体チップ及び半導体装置 |
KR101448150B1 (ko) * | 2007-10-04 | 2014-10-08 | 삼성전자주식회사 | 메모리 칩이 적층된 멀티 칩 패키지 메모리, 메모리 칩의적층 방법 및 멀티 칩 패키지 메모리의 동작 제어 방법 |
KR101393311B1 (ko) * | 2008-03-19 | 2014-05-12 | 삼성전자주식회사 | 프로세스 변화량을 보상하는 멀티 칩 패키지 메모리 |
JP5647014B2 (ja) * | 2011-01-17 | 2014-12-24 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
JP2012155814A (ja) * | 2011-01-28 | 2012-08-16 | Elpida Memory Inc | 半導体装置及びこれを備える情報処理システム |
JP5710992B2 (ja) * | 2011-01-28 | 2015-04-30 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
US9432298B1 (en) * | 2011-12-09 | 2016-08-30 | P4tents1, LLC | System, method, and computer program product for improving memory systems |
JP2012226794A (ja) * | 2011-04-18 | 2012-11-15 | Elpida Memory Inc | 半導体装置、及び半導体装置の制御方法。 |
KR20130042078A (ko) * | 2011-10-18 | 2013-04-26 | 에스케이하이닉스 주식회사 | 반도체 장치 |
KR102058509B1 (ko) * | 2012-06-29 | 2019-12-24 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
JP2015149340A (ja) * | 2014-02-05 | 2015-08-20 | マイクロン テクノロジー, インク. | 半導体装置 |
KR20160068546A (ko) * | 2014-12-05 | 2016-06-15 | 에스케이하이닉스 주식회사 | 반도체 장치의 입력 회로 및 이를 이용한 반도체 시스템 |
US9570142B2 (en) * | 2015-05-18 | 2017-02-14 | Micron Technology, Inc. | Apparatus having dice to perorm refresh operations |
JP2018032141A (ja) | 2016-08-23 | 2018-03-01 | 東芝メモリ株式会社 | 半導体装置 |
US10020046B1 (en) * | 2017-03-03 | 2018-07-10 | Micron Technology, Inc. | Stack refresh control for memory device |
KR20200016681A (ko) * | 2018-08-07 | 2020-02-17 | 삼성전자주식회사 | 스택 구조의 다이들을 포함하는 반도체 장치 및 그 테스트 방법 |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4252485B2 (ja) | 2004-03-29 | 2009-04-08 | 富士通マイクロエレクトロニクス株式会社 | スイッチングレギュレータ制御回路、スイッチングレギュレータ、およびスイッチングレギュレータ制御方法 |
JP2012243251A (ja) | 2011-05-24 | 2012-12-10 | Elpida Memory Inc | メモリシステム |
US20180374779A1 (en) | 2017-06-21 | 2018-12-27 | SK Hynix Inc. | Semiconductor device |
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