CN112117267A - 具有中介层的层叠半导体封装件 - Google Patents
具有中介层的层叠半导体封装件 Download PDFInfo
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- CN112117267A CN112117267A CN201911081481.2A CN201911081481A CN112117267A CN 112117267 A CN112117267 A CN 112117267A CN 201911081481 A CN201911081481 A CN 201911081481A CN 112117267 A CN112117267 A CN 112117267A
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- pad
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- interposer
- pads
- upper chip
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 230000005540 biological transmission Effects 0.000 claims description 13
- 239000010410 layer Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000007792 addition Methods 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
具有中介层的层叠半导体封装件。根据本公开的一方面的半导体封装件包括:封装基板;顺序层叠在封装基板上的下芯片、中介层和上芯片;以及电连接封装基板和中介层的接合布线。中介层包括:在中介层的下表面上电连接至下芯片的下芯片连接焊盘;在中介层的上表面上分别电连接至上芯片的第一上芯片连接焊盘和第二上芯片连接焊盘;设置在中介层的上表面上并接合至接合布线的布线接合焊盘;设置在中介层的上表面上并且将第二上芯片连接焊盘电连接至布线接合焊盘的第一重分布线;以及将下芯片连接焊盘电连接至第一上芯片连接焊盘的通孔电极。
Description
技术领域
本公开总体上涉及半导体封装件,并且更具体地,涉及包括中介层(interposer)的层叠半导体封装件。
背景技术
通常,半导体封装件可以被配置为包括基板和安装在基板上的半导体芯片。半导体芯片可以通过诸如凸块或布线之类的连接构件电连接至基板。
近来,根据对具有高性能和高集成度的半导体封装件的需求,已经提出了在基板上层叠多个半导体芯片的各种方式。例如,已经提出了使用过硅通孔(TSV)电连接层叠在基板上的多个半导体芯片的技术。
发明内容
根据本公开的实施方式,半导体封装件可以包括:封装基板;顺序层叠在封装基板上的下芯片、中介层和上芯片;并且包括电连接封装基板和中介层的接合布线。中介层包括设置在中介层的下表面上的下芯片连接焊盘,其中,下芯片连接焊盘电连接至下芯片。中介层还包括设置在中介层的上表面上的第一上芯片连接焊盘和第二上芯片连接焊盘,其中,第一上芯片连接焊盘和第二上芯片连接焊盘电连接至上芯片。中介层还包括设置在中介层的上表面上并接合至接合布线的布线接合焊盘;设置在中介层的上表面上并将第二上芯片连接焊盘电连接至布线接合焊盘的第一重分布线;以及将下芯片连接焊盘电连接至第一上芯片连接焊盘的通孔电极。
根据本公开的另一实施方式,层叠半导体封装件可以包括:封装基板;顺序层叠在封装基板上的下芯片、中介层和上芯片;以及电连接封装基板和中介层的接合布线。中介层包括:将下芯片电连接至上芯片的通孔电极;以及将上芯片电连接至接合布线的第一重分布线。
附图说明
图1是例示根据本公开的实施方式的半导体封装件的截面图。
图2是例示根据本公开的实施方式的半导体芯片的平面图。
图3是例示根据本公开的实施方式的半导体芯片的平面图。
图4A、图4B和图4C是例示根据本公开的实施方式的中介层的图。
图5是例示根据本公开的实施方式的在半导体芯片与封装基板之间交换电信号的方法的示意图。
图6是例示根据本公开的实施方式的半导体封装件的内部电路配置的图。
具体实施方式
本文使用的术语可以对应于考虑到它们在实施方式中的功能而选择的词,并且根据实施方式所属领域的普通技术人员,可以将术语的含义解释为不同。如果详细定义了术语,则可以根据这些定义来解释术语。除非另有定义,否则本文中使用的术语(包括技术术语和科学术语)具有与实施方式所属领域的普通技术人员通常所理解的含义相同的含义。
将理解的是,尽管在本文中可以使用术语“第一”、“第二”、“第三”等来描述各种元件,但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一元件区分开,而不用于暗示元件的特定顺序或数量。还应理解,当元件或层称为在另一元件或层“上”、“上方”、“下”、“下方”或“外部”时,该元件或层可以直接接触另一个元件或层,或者可以存在中间元件或层。应该以类似的方式来解释用于描述元件或层之间的关系的其它词语(例如,“在……之间”与“直接在……之间”或“相邻”与“直接相邻”)。
诸如“之下”、“下”、“低于”、“上方”、“高于”、“顶”、“底”等的空间相对术语可以用于描述元件和/或特征与另一元件和/或特征的关系,如例如附图中示出的关系。将理解的是,除了附图中绘出的方位之外,空间相对术语还旨在涵盖装置在使用和/或操作中的不同方位。例如,当附图中的装置被翻转时,则被描述为在其它元件或特征下或下方的元件将被定向在其它元件或特征上方。可以以其它方式定向装置(旋转90度或其它方位),并据此解释本文中使用的空间相对描述语。
本文描述的半导体封装件可以包括诸如半导体芯片的电子装置。可以通过使用管芯切割工艺将诸如晶圆之类的半导体基板分成多片来获得半导体芯片。半导体芯片可以对应于存储器芯片、逻辑芯片(包括专用集成电路(ASIC)芯片)或片上***(SoC)。存储器芯片可以包括集成在半导体基板上的动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、NAND型闪存电路、NOR型闪存电路、磁随机存取存储器(MRAM)电路、电阻式随机存取存储器(ReRAM)电路、铁电随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)电路。逻辑芯片可以包括集成在半导体基板上的逻辑电路。半导体芯片根据它们在管芯切割工艺之后的形状可以被称为半导体管芯。
半导体封装件可以包括其上安装有半导体芯片的封装基板。封装基板可以包括集成电路图案的至少一层,并且在本说明书中可以称为印刷电路板(PCB)。
作为实施方式,半导体封装件可以包括安装在封装基板上的多个半导体芯片。在半导体封装件中,多个半导体芯片中的任何一个可以被设置为主芯片,而其余半导体芯片可以被设置为从芯片。然后,可以使用主芯片来控制从芯片的存储器单元。主芯片可以直接与封装基板交换信号,而从芯片可以通过主芯片与封装基板交换信号。
半导体封装件可用于诸如移动电话、与生物技术或医疗保健相关的电子***、或可穿戴电子***之类的各种通信***中。
在整个说明书中,相同的附图标记指代相同的元件。即使未参照一附图提及或描述附图标记,也可以参照另一附图提及或描述该附图标记。另外,即使附图标记未在一附图中示出,也可以参照另一附图来提及或描述附图标记。
图1是例示根据本公开的实施方式的半导体封装件1的截面图。
参照图1,半导体封装件1可以包括层叠在封装基板100上的下芯片200、中介层300和上芯片400。中介层300可以使用接合布线50a和50b电连接至封装基板100。
下芯片200和上芯片400可以各自是包括集成电路的半导体芯片。上芯片400可以使用第一重分布线340a和340b以及接合布线50a和50b电连接至封装基板100。此外,下芯片200可以使用中介层300中的通孔电极360a和360b电连接至上芯片400。也就是说,上芯片400可以通过第一重分布线340a和340b以及接合布线50a和50b与封装基板100交换电信号,并且下芯片200可以通过上芯片400与封装基板100交换电信号。
参照图1,提供了封装基板100。封装基板100可以具有上表面100S1和与上表面100S1相对的下表面100S2。尽管图1中未示出,但是封装基板100可以包括集成电路图案的至少一层。
用于与中介层300进行布线接合的连接焊盘110a和110b可以设置在封装基板100的上表面100S1上。另外,用于与其它半导体封装件或PCB的电连接的连接结构550可以设置在封装基板100的下表面100S2上。连接结构550可以包括例如凸块、焊球等。
下芯片200可以设置在封装基板100上。下芯片200可以具有上表面200S1和下表面200S2。第一下芯片焊盘210a和210b以及第二下芯片焊盘220a和220b可以设置在下芯片200的上表面200S1上。第一下芯片焊盘210a和210b中的每个可以通过第一凸块520分别连接至中介层300的下芯片连接焊盘350a和350b。第二下芯片焊盘220a和220b可以在横向方向(即,x方向)上与第一下芯片焊盘210a和210b间隔开设置并且可以不参与与中介层300的横向连接。此外,非导电粘合层510可以设置在下芯片200的下表面200S2上,使得下芯片200可以接合至封装基板100。
中介层300可以设置在下芯片200上方。中介层300可以具有上表面300S1和下表面300S2。电连接至下芯片200的下芯片连接焊盘350a和350b可以设置在中介层300的下表面300S2上。在实施方式中,下芯片连接焊盘350a和350b可以通过第一凸块520分别连接至第一下芯片焊盘210a和210b。电连接至上芯片400的第一上芯片连接焊盘310a和310b以及第二上芯片连接焊盘320a和320b可以设置在中介层300的上表面300S1上。
中介层300可以包括在横向方向(即,D1和D2方向)上从上芯片400的边缘区域突出的至少一个区域。因此,作为示例,中介层300沿x方向的宽度可以大于上芯片400沿x方向的宽度。布线接合焊盘330a和330b可以设置在中介层300的在横向方向上突出或延伸超出上芯片400的区域上。布线接合焊盘330a和330b可以通过接合布线50a和50b电连接至封装基板100上的下芯片连接焊盘110a和110b。此外,用于将第二上芯片连接焊盘320a和320b连接至布线接合焊盘330a和330b的第一重分布线340a和340b可以设置在中介层300的上表面300S1上。第二上芯片连接焊盘320a和320b电连接至上芯片400的第二上芯片焊盘420a和420b,使得上芯片400通过第一重分布线340a和340b以及接合布线50a和50b电连接至封装基板100。
中介层300可以包括用于将第一上芯片连接焊盘310a和310b分别电连接至下芯片连接焊盘350a和350b的通孔电极360a和360b。在实施方式中,如下面参照图5所述,中介层300还可以包括设置在中介层300的上表面300S1和下表面300S2上的第二布线层至第五布线层371、372、381和382,以便将第一上芯片连接焊盘310a和310b以及下芯片连接焊盘350a和350b分别连接至通孔电极360a和360b。
上芯片400可以设置在中介层300上方。上芯片400可以具有上表面400S1和下表面400S2。第一上芯片焊盘410a和410b以及第二上芯片焊盘420a和420b可以设置在上芯片400的面向中介层300的上表面400S1上。第一上芯片焊盘410a和410b可以通过第二凸块530分别连接至中介层300的第一上芯片连接焊盘310a和310b。第二上芯片焊盘420a和420b可以在横向方向(即,x方向)上与第一上芯片焊盘410a和410b间隔开设置,并可以通过第三凸块540分别连接至中介层300的第二上芯片连接焊盘320a和320b。在实施方式中,第一上芯片焊盘410a和410b中的每个可以具有与第二上芯片焊盘420a和420b基本上相同的尺寸。在实施方式中,第二凸块530和第三凸块540可以具有基本相同的尺寸。
在实施方式中,下芯片200和上芯片400中的每个可以是存储器芯片。在实施方式中,下芯片200和上芯片400可以是具有相同结构的芯片。在实施方式中,上芯片400可以是主芯片,并且下芯片200可以是从芯片。上芯片400可以通过中介层300的第一重分布线340a和340b以及接合布线50a和50b电连接至封装基板100。下芯片200可以借助于通孔电极360a和360b通过上芯片400电连接至封装基板100。因此,下芯片200可以共享上芯片400的输入/输出电路。
图2和图3是例示根据本公开的实施方式的半导体芯片的平面图。更具体地,图2例示了图1的下芯片200,并且图3例示了图1的上芯片400。图4A、图4B和图4C是例示根据本公开的实施方式的中介层的图。更具体地,图4A是例示图1的中介层300的平面图,图4B是图4A的部分“L”的局部放大图,并且图4C是图4A的通孔布置区域“C”的立体图。
参照图2,下芯片200可以具有沿x方向的短轴和沿y方向的长轴。另外,下芯片200可以具有平行于长轴的中心轴Cy-200。下芯片200可以在短轴方向上具有宽度W200,并且在长轴方向上具有长度L200。中心轴Cy-200可以延伸以使得下芯片200的宽度W200的一半在中心轴Cy-200的各侧上。
第一下芯片焊盘210a和210b以及第二下芯片焊盘220a和220b可以沿长轴方向(即,y方向)布置。第一下芯片焊盘210a和210b以及第二下芯片焊盘220a和220b可以设置为分别相对于中心轴Cy-200形成对称对。在具体实施方式中,第一下芯片焊盘210a和210b可以设置为比第二下芯片焊盘220a和220b更靠近中心轴Cy-200。第一下芯片焊盘210a和210b可以相对于中心轴Cy-200分类为第一下芯片左焊盘210a和第一下芯片右焊盘210b。第二下芯片焊盘220a和220b可以相对于中心轴Cy-200分类为第二下芯片左焊盘220a和第二下芯片右焊盘220b。
如图2所示,第一下芯片焊盘210a和210b中的每个的表面积可以与第二下芯片焊盘220a和220b中的每个的表面积基本相同。作为示例,第一下芯片焊盘210a和210b以及第二下芯片焊盘220a和220b可以具有相同的形状和尺寸。这里,第一下芯片焊盘210a和210b的行以及第二下芯片焊盘220a和220b的行可以在x方向上以相同的水平间隔S1布置。如图2所示,第二下芯片左焊盘220a、第一下芯片左焊盘210a、第一下芯片右焊盘210b和第二下芯片右焊盘220b可以以相同的水平间隔S1顺序布置。另外,第一下芯片焊盘210a和210b以及第二下芯片焊盘220a和220b可以在y方向上以相同的垂直间隔S2布置。
参照图1和图2,第一下芯片焊盘210a和210b可以通过通孔电极360a和360b电连接至上芯片400。也就是说,第一下芯片焊盘210a和210b可以用作下芯片200的用于与上芯片400交换电信号的信号输入/输出焊盘。第一下芯片焊盘210a和210b可以以集中方式布置在下芯片200的上表面200S1上的通孔电极布置区A中。第二下芯片焊盘220a和220b可以沿中心轴Cy-200以相同的垂直间隔S2连续设置。此外,下芯片200的第二下芯片焊盘220a和220b可以不电连接至诸如中介层300和封装基板100之类的其它结构。
参照图3,上芯片400可具有沿x方向的短轴和沿y方向的长轴。另外,上芯片400可以具有与长轴平行的中心轴Cy-400。上芯片400可以在短轴方向上具有宽度W400,并且可以在长轴方向上具有长度L400。中心轴Cy-400可以延伸以使得上芯片400的宽度W400的一半在中心轴Cy-400的各侧上。
第一上芯片焊盘410a和410b以及第二上芯片焊盘420a和420b可以沿长轴方向(即,y方向)布置在上芯片400的上表面400S1上。第一上芯片焊盘410a和410b以及第二上芯片焊盘420a和420b可以布置为分别相对于中心轴Cy-400形成对称对。在具体示例中,第一上芯片焊盘410a和410b可以设置为比第二上芯片焊盘420a和420b更靠近中心轴Cy-400。第一上芯片焊盘410a和410b可以相对于中心轴Cy-400分类为第一上芯片左焊盘410a和第一上芯片右焊盘410b。第二上芯片焊盘420a和420b可以相对于中心轴Cy-400分类为第二上芯片左焊盘420a和第二上芯片右焊盘420b。
如图3所示,第一上芯片焊盘410a和410b中的每个的表面积可以与第二上芯片焊盘420a和420b中的每个的表面积基本相同。作为示例,第一上芯片焊盘410a和410b以及第二上芯片焊盘420a和420b可以具有相同的形状和尺寸。这里,第一上芯片焊盘410a和410b的行以及第二上芯片焊盘420a和420b的行可以在x方向上以相同的水平间隔S1布置。如图3所示,第二上芯片左焊盘420a、第一上芯片左焊盘410a、第一上芯片右焊盘410b和第二上芯片右焊盘420b可以以相同的水平间隔S1顺序地布置。另外,第一上芯片焊盘410a和410b以及第二上芯片焊盘420a和420b可以在y方向上以相同的垂直间隔S2布置。
参照图1和图3,第一上芯片焊盘410a和410b可以通过通孔电极360a和360b电连接至下芯片200。也就是说,第一上芯片焊盘410a和410b可以用作上芯片400的用于与下芯片200交换电信号的信号输入/输出焊盘。第一上芯片焊盘410a和410b可以以集中方式布置在上芯片400的上表面400S1上的通孔电极布置区B中。第二上芯片焊盘420a和420b可以沿中心轴Cy-400以相同的垂直间隔S2连续地设置。上芯片400的第二上芯片焊盘420a和420b可以电连接至中介层300的第二上芯片连接焊盘320a和320b。也就是说,第二上芯片焊盘420a和420b可以用作上芯片400的用于与中介层300和封装基板100交换电信号的信号输入/输出焊盘。
参照图4A至图4C,中介层300可以具有沿x方向的短轴和沿y方向的长轴。另外,中介层300可以具有平行于长轴的中心轴Cy-300。中介层300可以在短轴方向上具有宽度W300,并且可以在长轴方向上具有长度L300。中心轴Cy-300可以延伸以使得中介层300的宽度W300的一半在中心轴Cy-300的各侧上。
第一上芯片连接焊盘310a和310b、第二上芯片连接焊盘320a和320b以及布线接合焊盘330a和330b可以沿长轴方向(即,y方向)布置在中介层300的上表面300S1上。在实施方式中,第一上芯片连接焊盘310a和310b、第二上芯片连接焊盘320a和320b以及布线接合焊盘330a和330b可以设置为分别相对于中心轴Cy-300形成对称对。在具体示例中,第一上芯片连接焊盘310a和310b、第二上芯片连接焊盘320a和320b以及布线接合焊盘330a和330b可以在x方向上从中介层300的中心轴Cy-300开始顺序地设置。如图所示,第一上芯片连接焊盘310a和310b、第二上芯片连接焊盘320a和320b以及布线接合焊盘330a和330b中的每个的表面积可以基本相同。作为示例,第一上芯片连接焊盘310a和310b、第二上芯片连接焊盘320a和320b以及布线接合焊盘330a和330b可以具有相同的形状和尺寸。
此外,第一上芯片连接焊盘310a和310b可以被分类为相对于中心轴Cy-300彼此对称的第一上左焊盘310a和第一上右焊盘310b。这里,连接至第一上左焊盘310a的第二重分布线371和连接至第一上右焊盘310b的第三重分布线372可以沿y方向设置在中介层300的上表面300S1上。如以下参照图4C至图5所描述的,第二重分布线371可以将第一上左焊盘310a连接至第一通孔电极360a,并且第三重分布线372可以将第一上右焊盘310b连接至第二通孔电极360b。布线接合焊盘330a和330b可以被分类为相对于中心轴Cy-300彼此对称的左布线接合焊盘330a和右布线接合焊盘330b。
此外,第一上芯片连接焊盘310a和310b可以通过第二凸块530分别连接至第一上芯片焊盘410a和410b。
下芯片连接焊盘350a和350b可以设置在中介层300的下表面300S2上。下芯片连接焊盘350a和350b可以通过第一凸块520分别连接至下芯片200的第一下芯片焊盘210a和210b。此外,下芯片连接焊盘350a和350b可以分类为相对于中心轴Cy-300彼此对称的下左焊盘350a和下右焊盘350b。这里,连接至下左焊盘350a的第五重分布线382和连接至下右焊盘350b的第四重分布线381可以设置在中介层300的下表面300S2上。
下左焊盘350a可以在中介层300的下表面300S2上通过第五重分布线382连接至第二通孔电极360b。另外,下右焊盘350b可以通过第四重布线381连接至第一通孔电极360a。在实施方式中,下左焊盘350a可以直接设置在上左焊盘310a的下方以面对上左焊盘310a。另外,下右焊盘350b可以直接设置在上右焊盘310b的下方以面对上右焊盘310b。换句话说,下左焊盘350a和上左焊盘310a可以设置为在垂直方向上彼此交叠,并且下右焊盘350b和上右焊盘310b可以设置为在垂直方向上彼此交叠。
参照图1和图4A,第一重分布线340a和340b可以设置在中介层300的上表面300S1上。第一重分布线340a和340b可以成对设置,以相对于中心轴Cy-300对称。作为示例,第一重分布线340a和340b可以相对于中心轴Cy-300分类为第一左重分布线340a和第一右重分布线340b。第一重分布线340a和340b可以将第二上芯片连接焊盘320a和320b分别连接至布线接合焊盘330a和330b。更具体地,第一重分布线340a和340b可以设置在第二上芯片连接焊盘320a和320b与布线接合焊盘330a和330b之间,同时在短轴方向(即,x方向)上延伸。
图5是例示根据本公开的实施方式的在半导体芯片与封装基板之间交换电信号的方法的示意图。在图5,使用上面参照图1至图4C描述的半导体封装件1的下芯片200、中介层300和上芯片400的构造来例示交换电信号的方法。为了便于说明,在图5中未示出封装基板100。
参照图5,上芯片400和下芯片200之间的电信号交换可以如下进行。作为示例,从上芯片400的第一上芯片左焊盘410a输出的电信号可以通过第二凸块530,中介层300的第一上左焊盘310a、第二重分布线371、第一通孔电极360a、第三重分布线381和下右焊盘350b,以及第一凸块520到达第一下芯片右焊盘210b。这样,半导体封装件1可以具有从上芯片400至下芯片200的电信号路径。另外,半导体封装件1可以具有在相反方向上从下芯片200至上芯片400的电信号路径。上芯片400和下芯片200之间的电信号路径在图5中示为“F1”。
作为另一示例,从上芯片400的第一上芯片右焊盘410b输出的电信号也可以通过第二凸块530,中介层300的第一上右焊盘310b、第三重分布线372、第二通孔电极360b、第四重分布线382和下左焊盘350a,以及第一凸块520到达第一下芯片左焊盘210a。这样,半导体封装件1可以具有从上芯片400至下芯片200的电信号路径。另外,半导体封装件1可以具有在相反方向上从下芯片200至上芯片400的电信号路径。
参照图5和图1,上芯片400和封装基板100之间的电信号交换可以如下进行。作为示例,从上芯片400的第二上芯片左焊盘420a输出的电信号可以通过第三凸块540、中介层300的第二上左焊盘320a和第一左重分布线340a到达左布线接合焊盘330a。到达左布线接合焊盘330a的电信号可以通过接合布线50a和50b中的左布线50a传输至封装基板100。这样,半导体封装件1可以具有从上芯片400至封装基板100的电信号路径。电信号可以在相反方向上从封装基板100传输至上芯片400。上芯片400和封装基板100之间的电信号路径在图5中示为“F2”。
作为另一示例,从第二上芯片右焊盘420b输出的电信号也可以通过第三凸块540、中介层300的第二上右焊盘320b和第一右重分布线340b到达右布线接合焊盘330b。到达右布线接合焊盘330b的电信号可以通过接合布线50a和50b中的右布线50b传输至封装基板100。
如上所述,上芯片400可以不通过布线接合直接连接至封装基板100。替代地,在使用凸块将上芯片400连接至中介层300之后,上芯片400可以电连接至设置在中介层300上的布线接合焊盘340a和340b。因此,上芯片400可以通过接合至布线接合焊盘340a和340b的接合布线50a和50b电连接至封装基板100。
另外,下芯片200可以不直接连接至封装基板100,而是可以经由上芯片400电连接至封装基板100。也就是说,下芯片200可以不直接具有用于与封装基板100布线接合的布线接合焊盘。下芯片200可以使用中介层300的通孔电极360a和360b连接至上芯片400,然后使用上芯片400的内部布线电连接至第二上芯片焊盘420a和420b。也就是说,下芯片200可以共享作为上芯片400的输入/输出焊盘的第二上芯片焊盘420a和420b,从而下芯片200可以使用与上芯片400的电信号路径相同的路径与封装基板100交换电信号。
图6是例示根据本公开的实施方式的半导体封装件的内部电路构造的图。图6可以是示意性地例示以上参照图1描述的半导体封装件1的内部电路的图。
参照图6,封装基板100可以包括设置在上表面100S1上并且通过接合布线50a和50b连接的连接焊盘110a和110b。另外,封装基板100可以包括连接结构550,连接结构550设置在下表面100S2上并且设置为用于与另一半导体封装件或印刷电路板的电连接。
下芯片200可以包括第一输入/输出电路块200A1和第二输入/输出电路块200A2、第一地址和命令电路块200B1、第一数据传输电路块200B2和第一存储器单元核心块200C。同样,上芯片400可以包括第三输入/输出电路块400A1和第四输入/输出电路块400A2、第二地址和命令电路块400B1、第二数据传输电路块400B2、和第二存储器单元核心块400C。
设置在下芯片200和上芯片400之间的中介层300可以包括设置在中介层300的下表面300S2上的用于与下芯片200连接的下芯片连接焊盘350a和350b。另外,中介层300可以包括设置在中介层300的上表面300S1上的用于与上芯片400连接的第一上芯片连接焊盘310a和310b以及第二上芯片连接焊盘320a和320b。另外,中介层300可以包括用于与接合布线50a和50b连接的布线接合焊盘330a和330b,并且可以包括用于将第二上芯片连接焊盘320a和320b分别连接至布线接合焊盘330a和330b的第一重分布线340a和340b。
首先,封装基板100的电信号可以经由连接焊盘110a和110b,接合布线50a和50b,中介层300的布线接合焊盘330a和330b、第一重分布线340a和340b和第二上芯片连接焊盘320a和320b,以及第三凸块540输入至上芯片400的第二上芯片焊盘420a和420b。在输入电信号当中,沿着输入电信号的第一上芯片内部布线400I1的一些输入信号可以穿过第三输入/输出电路块400A1并由第二地址和命令电路块400B1转换为地址和命令信号,然后可以传送至第二存储器单元核心块400C。另外,在输入电信号当中,沿着第二上芯片内部布线400I2的一些其它输入信号可以穿过第四输入/输出电路块400A2,并由第二数据传输电路块400B2转换为数据信号,然后可以传送至第二存储器单元核心块400C。
此外,上芯片400的第一上芯片内部布线400I1可以经由第一上芯片焊盘410a、第二凸块530、中介层300的第一上芯片连接焊盘310a、中介层300的第一内部布线360a1(包括通孔电极和重分布线)、下芯片连接焊盘350b、第一凸块520和第一下芯片焊盘210b连接至第一下芯片内部布线200I1。因此,在封装基板100的电信号当中,从上芯片400的第二地址和命令电路块400B1输出的一些电信号可以输入至下芯片200。输入至下芯片200的电信号可以输入至第一地址和命令电路块200B1并转换成第一地址和命令信号,然后可以沿着第一下芯片内部布线200I1传送至第一存储器单元核心块200C。结果,下芯片200能够经由上芯片400接收封装基板100的电信号,而无需电信号穿过第二下芯片焊盘220b、第一输入/输出电路块200A1、和第一地址和命令电路块200B1。
同样地,上芯片400的第二上芯片内部布线400I2可以经由第一上芯片焊盘410b、第二凸块530、中介层300的第一上芯片连接焊盘310b、中介层300的第二内部布线360b1(包括通孔电极和重分布线)、下芯片连接焊盘350a、第一凸块520、第一下芯片焊盘210a连接至第二下芯片内部布线200I2。因此,在封装基板100的电信号当中,从上芯片400的第二数据传输电路块400B2输出的一些电信号可以输入至下芯片200。输入至下芯片200的电信号可以输入至第一数据传输电路块200B2中并转换为数据信号,然后可以沿着第二下芯片内部布线200I2传送至第一存储器单元核心块200C。结果,下芯片200能够经由上芯片400接收封装基板100的电信号,而无需电信号穿过第二下芯片焊盘220a、第二输入/输出电路块200A2以及第一数据传输电路块200B2。
此外,再次参照图6,从上芯片400的第二数据单元核心块400C输出的电信号可以沿着第一上芯片内部布线400I1穿过第二地址和命令电路块400B1和第三输入/输出电路块400A1,或者可以沿着第二上芯片内部布线400I2穿过第二数据传输电路块400B2和第四输入/输出电路块400A2,从而到达第二上芯片焊盘420a或420b。此后,电信号可以从第二上芯片焊盘420a和420b输出至中介层300。并且,电信号可以通过接合布线50a和50b从中介层300传送至封装基板100。
另外,从下芯片200的第一数据单元核心块200C输出的电信号可以分别沿着第一下芯片内部布线200I1和第二下芯片内部布线200I2、第一中介层内部布线360a1和第二中介层内部布线360b1到达第一上芯片连接焊盘310a和310b。信号可以沿着第一上芯片内部布线400I1和第二上芯片内部布线400I2移动并到达上芯片400的第二上芯片焊盘420a和420b。此后,电信号可以从第二上芯片焊盘420a和420b输出至中介层300,并且然后可以经由接合布线50a和50b传送至封装基板100。
电连接至下芯片200的第一下芯片内部布线200I1和第二下芯片内部布线200I2的第二下芯片焊盘220a和220b可以不电连接至封装件外部的其它结构。因此,除了上芯片400之外,下芯片200可以不通过第一输入/输出电路块200A1和第二输入/输出电路块200A2电连接至其它外部芯片、封装件或基板。
如上所述,本公开的实施方式可以提供具有顺序地层叠在封装基板上的下芯片、中介层和上芯片的半导体封装件。在半导体封装件中,中介层可以通过接合布线连接至封装基板。上芯片可以通过凸块连接至中介层,并且可以经由重分布线和接合布线电连接至封装基板。另外,上芯片可以使用中介层内部的通孔电极电连接至下芯片。
根据本公开的实施方式,在上芯片和下芯片上能够省略用于与封装基板连接的重分布线。因此,可以减少或抑制上芯片和下芯片的重分布线与电路图案层之间的寄生电容的产生。另外,上芯片可以被配置为经由中介层与封装基板交换电信号,而下芯片可以被配置为经由上芯片与封装基板交换电信号。因此,能够省略下芯片和封装基板之间的直接电连接,结果,能够进一步减小或抑制由于电连接中所涉及的输入/输出电路而在下芯片中产生的寄生电容。
因此,在本公开的实施方式中,可以提供一种能够通过减少或抑制在层叠在封装基板上的半导体芯片中出现的不期望的寄生电容来提高半导体封装件的信号传输速度的半导体封装件结构。
已经出于示例性目的公开了本公开的实施方式。本领域技术人员将理解,在不脱离本公开和所附权利要求的范围和精神的情况下,可以进行各种变型、添加和替换。
相关申请的交叉引用
本申请要求于2019年6月21日提交的韩国专利申请No.10-2019-0074338的优先权,其全部内容通过引用合并于此。
Claims (24)
1.一种层叠半导体封装件,该层叠半导体封装件包括:
封装基板;
顺序层叠在所述封装基板上的下芯片、中介层和上芯片;以及
接合布线,所述接合布线电连接所述封装基板和所述中介层,
其中,所述中介层包括:
下芯片连接焊盘,所述下芯片连接焊盘设置在所述中介层的下表面上,其中,所述下芯片连接焊盘电连接至所述下芯片;
第一上芯片连接焊盘和第二上芯片连接焊盘,所述第一上芯片连接焊盘和所述第二上芯片连接焊盘设置在所述中介层的上表面上,其中,所述第一上芯片连接焊盘和所述第二上芯片连接焊盘电连接至所述上芯片;
布线接合焊盘,所述布线接合焊盘设置在所述中介层的所述上表面上并接合至所述接合布线;
第一重分布线,所述第一重分布线设置在所述中介层的所述上表面上,所述第一重分布线将所述第二上芯片连接焊盘电连接至所述布线接合焊盘;以及
通孔电极,所述通孔电极将所述下芯片连接焊盘电连接至所述第一上芯片连接焊盘。
2.根据权利要求1所述的层叠半导体封装件,
其中,所述下芯片包括电连接至所述下芯片连接焊盘的第一下芯片焊盘,
其中,所述下芯片包括与所述第一下芯片焊盘横向相邻设置的第二下芯片焊盘,其中,所述第二下芯片焊盘未连接至所述下芯片连接焊盘且未连接至所述封装基板,并且
其中,所述上芯片包括电连接至所述第一上芯片连接焊盘的第一上芯片焊盘和电连接至所述第二上芯片连接焊盘的第二上芯片焊盘。
3.根据权利要求2所述的层叠半导体封装件,该层叠半导体封装件还包括:
第一凸块,所述第一凸块设置在所述第一下芯片连接焊盘和所述第一下芯片焊盘之间;
第二凸块,所述第二凸块设置在所述第一上芯片连接焊盘和所述第一上芯片焊盘之间;以及
第三凸块,所述第三凸块设置在所述第二上芯片连接焊盘和所述第二上芯片焊盘之间,
其中,所述第二凸块和所述第三凸块具有基本相同的尺寸。
4.根据权利要求2所述的层叠半导体封装件,其中,所述第一上芯片焊盘和所述第二上芯片焊盘具有基本相同的尺寸。
5.根据权利要求2所述的层叠半导体封装件,
其中,所述上芯片通过所述中介层电连接至所述封装基板,并且
其中,所述下芯片借助于所述中介层的所述通孔电极和所述上芯片电连接至所述封装基板。
6.根据权利要求2所述的层叠半导体封装件,
其中,所述下芯片包括:
第一地址和命令电路块,所述第一地址和命令电路块电连接至所述第一下芯片焊盘中的第一个下芯片焊盘;
第一数据传输电路块,所述第一数据传输电路块电连接至所述第一下芯片焊盘中的第二个下芯片焊盘;
第一输入/输出电路块,所述第一输入/输出电路块电连接至所述第二下芯片焊盘中的第一个下芯片焊盘并且电连接至所述第一地址和命令电路块;
第二输入/输出电路块,所述第二输入/输出电路块电连接至所述第二下芯片焊盘中的第二个下芯片焊盘并且电连接至所述第一数据传输电路块;以及
第一存储器单元核心块,所述第一存储器单元核心块电连接至所述第一地址和命令电路块并且电连接至所述第一数据传输电路块,并且
其中,所述上芯片包括:
第二地址和命令电路块,所述第二地址和命令电路块电连接至所述第一上芯片焊盘中的第一个上芯片焊盘;
第二数据传输电路块,所述第二数据传输电路块电连接至所述第一上芯片焊盘中的第二个上芯片焊盘;
第三输入/输出电路块,所述第三输入/输出电路块电连接至所述第二上芯片焊盘中的第一个上芯片焊盘并且电连接至所述第二地址和命令电路块;
第四输入/输出电路块,所述第四输入/输出电路块电连接至所述第二上芯片焊盘中的第二个上芯片焊盘并且电连接至所述第二数据传输电路块;以及
第二存储器单元核心块,所述第二存储器单元核心块电连接至所述第二地址和命令电路块并且电连接至所述第二数据传输电路块。
7.根据权利要求6所述的层叠半导体封装件,
其中,来自所述封装基板的第一电信号通过所述接合布线中的第一接合布线、所述布线接合焊盘中的第一布线接合焊盘、所述第一重分布线中的第一条重分布线、所述第二上芯片连接焊盘中的第一个上芯片连接焊盘、和所述第二上芯片焊盘中的第一个上芯片焊盘输入至所述第三输入/输出电路块,
其中,来自所述封装基板的第二电信号通过所述接合布线中的第二接合布线、所述布线接合焊盘中的第二布线接合焊盘、所述第一重分布线中的第二条重分布线、所述第二上芯片连接焊盘中的第二个上芯片连接焊盘、和所述第二上芯片焊盘中的第二个上芯片焊盘输入至所述第四输入/输出电路块,
其中,所述第一电信号使用所述上芯片的内部布线通过所述第二地址和命令电路块被传送至所述上芯片的所述第二存储器单元核心块,并且
其中,所述第二电信号使用所述上芯片的所述内部布线通过所述第二数据传输电路块被传送至所述上芯片的所述第二存储器单元核心块。
8.根据权利要求7所述的层叠半导体封装件,
其中,来自所述封装基板的所述第一电信号被传送至所述第一下芯片焊盘中的第二个下芯片焊盘,
其中,来自所述封装基板的所述第二电信号被传送至所述第一下芯片焊盘中的第一个下芯片焊盘,
其中,所述第一电信号使用所述下芯片的内部布线通过所述第一地址和命令电路块被传送至所述下芯片的所述第一存储器单元核心块,并且
其中,所述第二电信号使用所述下芯片的所述内部布线通过所述第一数据传输电路块被传送至所述下芯片的所述第一存储器单元核心块。
9.根据权利要求1所述的层叠半导体封装件,其中,所述中介层包括超出所述上芯片的侧边缘的至少一个横向突出区域。
10.根据权利要求9所述的层叠半导体封装件,其中,所述布线接合焊盘设置在所述中介层的所述至少一个横向突出区域上。
11.根据权利要求1所述的层叠半导体封装件,其中,所述第一上芯片连接焊盘、所述第二上芯片连接焊盘、所述布线接合焊盘、所述下芯片连接焊盘以及所述通孔电极各自以相对于所述中介层的中心轴成对对称的方式设置。
12.根据权利要求11所述的层叠半导体封装件,
其中,所述中介层包括相对于所述中介层的所述中心轴彼此对称的第一上左焊盘和第一上右焊盘作为所述第一上芯片连接焊盘,并且包括位于紧接在所述第一上左焊盘下方的下左焊盘以及位于紧接在所述第一上右焊盘下方的下右焊盘作为所述下芯片连接焊盘,并且
其中,所述第一上左焊盘通过第一通孔电极电连接至所述下右焊盘,并且所述第一上右焊盘通过第二通孔电极电连接至所述下左焊盘。
13.根据权利要求12所述的层叠半导体封装件,其中,所述中介层具有在所述中介层的所述上表面上将所述第一上左焊盘电连接至所述第一通孔电极的第二重分布线以及将所述第二通孔电极电连接至所述上右焊盘的第三重分布线,并且具有在所述中介层的所述下表面上将所述下右焊盘电连接至所述第一通孔电极的第四重分布线以及将所述第二通孔电极电连接至所述下左焊盘的第五重分布线。
14.一种层叠半导体封装件,该层叠半导体封装件包括:
封装基板;
顺序层叠在所述封装基板上的下芯片、中介层和上芯片;以及
接合布线,所述接合布线电连接所述封装基板和所述中介层,
其中,所述中介层包括:
通孔电极,所述通孔电极将所述下芯片电连接至所述上芯片;以及
第一重分布线,所述第一重分布线将所述上芯片电连接至所述接合布线。
15.根据权利要求14所述的层叠半导体封装件,
其中,所述上芯片通过所述中介层电连接至所述封装基板,并且
其中,所述下芯片借助于所述中介层的所述通孔电极和所述上芯片电连接至所述封装基板。
16.根据权利要求14所述的层叠半导体封装件,
其中,所述中介层还包括:
下芯片连接焊盘,所述下芯片连接焊盘设置在所述中介层的下表面上,其中,所述下芯片连接焊盘电连接至所述下芯片;
第一上芯片连接焊盘和第二上芯片连接焊盘,所述第一上芯片连接焊盘和所述第二上芯片连接焊盘设置在所述中介层的上表面上,其中,所述第一上芯片连接焊盘和所述第二上芯片连接焊盘电连接至所述上芯片;以及
布线接合焊盘,所述布线接合焊盘设置在所述中介层的所述上表面上并接合至所述接合布线。
17.根据权利要求16所述的层叠半导体封装件,
其中,所述通孔电极将所述下芯片连接焊盘电连接至所述第一上芯片连接焊盘,并且
其中,所述第一重分布线将所述第二上芯片连接焊盘电连接至所述布线接合焊盘。
18.根据权利要求17所述的层叠半导体封装件,其中,所述第一上芯片连接焊盘、所述第二上芯片连接焊盘、所述布线接合焊盘、所述下芯片连接焊盘和所述通孔电极各自以相对于所述中介层的中心轴成对对称的方式设置。
19.根据权利要求18所述的层叠半导体封装件,
其中,所述中介层包括相对于所述中介层的所述中心轴彼此对称的第一上左焊盘和第一上右焊盘作为所述第一上芯片连接焊盘,并且包括位于紧接在所述第一上左焊盘下方的下左焊盘和位于紧接在所述第一上右焊盘下方的下右焊盘作为所述下芯片连接焊盘,并且
其中,所述第一上左焊盘通过第一通孔电极电连接至所述下右焊盘,并且所述第一上右焊盘通过第二通孔电极电连接至所述下左焊盘。
20.根据权利要求19所述的层叠半导体封装件,
其中,所述中介层具有在所述中介层的所述上表面上将所述第一上左焊盘电连接至所述第一通孔电极的第二重分布线以及将所述第二通孔电极电连接至所述上右焊盘的第三重分布线,并且具有在所述中介层的所述下表面上将所述下右焊盘电连接至所述第一通孔电极的第四重分布线以及将所述第二通孔电极电连接至所述下左焊盘的第五重分布线。
21.根据权利要求16所述的层叠半导体封装件,其中,所述布线接合焊盘设置在所述中介层的超出所述上芯片的边缘横向延伸的区域上。
22.根据权利要求16所述的层叠半导体封装件,
其中,所述下芯片包括电连接至所述下芯片连接焊盘的第一下芯片焊盘和与所述第一下芯片焊盘横向相邻设置的第二下芯片焊盘,其中,所述第二下芯片焊盘未连接至所述下芯片连接焊盘并且未连接至所述封装基板,并且
其中,所述上芯片包括电连接至所述第一上芯片连接焊盘的第一上芯片焊盘和电连接至所述第二上芯片连接焊盘的第二上芯片焊盘。
23.根据权利要求22所述的层叠半导体封装件,该层叠半导体封装件还包括:
第一凸块,所述第一凸块设置在所述下芯片连接焊盘和所述第一下芯片焊盘之间;
第二凸块,所述第二凸块设置在所述第一上芯片连接焊盘和所述第一上芯片焊盘之间;以及
第三凸块,所述第三凸块设置在所述第二上芯片连接焊盘和所述第二上芯片焊盘之间,
其中,所述第二凸块和所述第三凸块具有基本相同的尺寸。
24.根据权利要求22所述的层叠半导体封装件,其中,所述第一上芯片焊盘和所述第二上芯片焊盘具有基本相同的尺寸。
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- 2019-10-17 TW TW108137487A patent/TW202101726A/zh unknown
- 2019-10-22 US US16/660,671 patent/US20200402959A1/en not_active Abandoned
- 2019-11-07 CN CN201911081481.2A patent/CN112117267A/zh active Pending
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KR20200145387A (ko) | 2020-12-30 |
US20200402959A1 (en) | 2020-12-24 |
TW202101726A (zh) | 2021-01-01 |
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