JP7114873B2 - 半導体装置 - Google Patents
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- JP7114873B2 JP7114873B2 JP2017199338A JP2017199338A JP7114873B2 JP 7114873 B2 JP7114873 B2 JP 7114873B2 JP 2017199338 A JP2017199338 A JP 2017199338A JP 2017199338 A JP2017199338 A JP 2017199338A JP 7114873 B2 JP7114873 B2 JP 7114873B2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Description
[先行技術文献]
[特許文献]
[特許文献1] 特開2015-135954号公報
本例では、トランジスタ部70を半導体基板の下面側に投影した領域には、コレクタ領域22が設けられる。境界メサ部94‐1を半導体基板の下面側に投影した領域には、コレクタ領域22が設けられてよく、トランジスタ部70のコレクタ領域22が延伸して設けられてよい。この場合、境界メサ部94-1をトランジスタ部70の一部としてもよい。
コレクタ領域22のY軸正方向の端部P1を上面に投影した位置から、コンタクト領域15までの長さAは、ベース領域14の深さより長くてよく、ベース領域14からコレクタ領域22までの深さ方向の長さより長くてよい。本例では、100μmである。
蓄積領域16のY軸方向における外側の端部からゲート配線51のY軸方向における外側の端部までの長さL2は、ゲート配線51のY軸方向における外側の端部からライフタイムキラー領域19のY軸方向外側の端部までの長さL3より長くてよい。
トランジスタ部70‐1のコンタクト領域15のうち、ゲートトレンチ部40の第2部分48に隣接する端から、トランジスタ部70‐2のコンタクト領域15のうち、ゲートトレンチ部40の第2部分48に隣接する端までの、ゲートトレンチ部40の第2部分48を含む領域を、第2境界部74としてよい。
トランジスタ部70‐3のコンタクト領域15のうち、ゲートトレンチ部40の第2部分48に隣接する端から、ダイオード部80のダミートレンチ部30の第2部分38までの、ゲートトレンチ部40の第2部分48を含む領域を、第3境界部76としてよい。
図18に示すライフタイムキラー領域19は、再結合中心の濃度が極大(ピーク)となる位置を含んでよい。また、ライフタイムキラー領域19の深さ方向の幅は、導入されたヘリウム、点欠陥あるいは再結合中心のピーク濃度の半値全幅であってよい。再結合中心の濃度分布は、ピークを含む山型の分布形状を備えてよい。
Claims (25)
- 半導体基板と、
前記半導体基板に設けられたトランジスタ部と、
前記トランジスタ部に隣接して、前記半導体基板に設けられたダイオード部と
を備え、
前記ダイオード部は、
少なくとも一部が前記半導体基板の上面に露出する第2導電型のアノード領域と、
前記アノード領域の下方に設けられた第1導電型のドリフト領域と、
前記ドリフト領域の下方に設けられた第1導電型のカソード領域と、
前記アノード領域を少なくとも貫通して、予め定められた配列方向に沿って配列された複数のダミートレンチ部と、
前記半導体基板の上面に設けられ、コンタクトホールを有する層間絶縁膜と、
前記コンタクトホールに設けられ、前記配列方向とは異なる複数のダミートレンチ部の延伸方向に沿って設けられ、前記延伸方向において前記層間絶縁膜との境界である端部を有するコンタクト部と、
前記ドリフト領域の下方に設けられ、前記延伸方向における前記コンタクト部の外側の前記端部の直下に設けられる第2導電型の下面側半導体領域と
を有する、半導体装置。 - 前記コンタクト部の外側の前記端部は、前記配列方向において隣り合う前記ダミートレンチ部の前記延伸方向の端部よりも内側に設けられる、請求項1に記載の半導体装置。
- 前記ダイオード部は、前記延伸方向において前記アノード領域よりも外側に設けられ、前記半導体基板の上面から前記ダミートレンチ部よりも深くまで形成された第2導電型のウェル領域を有し、
前記コンタクト部の外側の前記端部は、前記ウェル領域よりも内側に設けられる、請求項1または2に記載の半導体装置。 - 半導体基板と、
前記半導体基板に設けられたトランジスタ部と、
前記トランジスタ部に隣接して、前記半導体基板に設けられたダイオード部と
を備え、
前記ダイオード部は、
少なくとも一部が前記半導体基板の上面に露出する第2導電型のアノード領域と、
前記アノード領域の下方に設けられた第1導電型のドリフト領域と、
前記ドリフト領域の下方に設けられた第1導電型のカソード領域と、
前記アノード領域を少なくとも貫通して、予め定められた配列方向に沿って配列された複数のダミートレンチ部と、
前記配列方向とは異なる複数のダミートレンチ部の延伸方向に沿って設けられたコンタクト部と、
前記ドリフト領域の下方に設けられ、前記延伸方向における前記コンタクト部の外側の端部の直下に設けられる第2導電型の下面側半導体領域と、
前記アノード領域と前記ドリフト領域との間とに設けられ、前記ドリフト領域よりも高い第1導電型のドーピング濃度を有する第1導電型の蓄積領域と、
を有し、
前記蓄積領域の前記延伸方向における外側の端部は、前記コンタクト部の前記延伸方向における外側の端部よりも内側に設けられ、
前記下面側半導体領域は、少なくとも前記コンタクト部の前記延伸方向における外側の端部の直下から前記蓄積領域の前記延伸方向の端部の直下まで連続して設けられる、半導体装置。 - 半導体基板と、
前記半導体基板に設けられたトランジスタ部と、
前記トランジスタ部に隣接して、前記半導体基板に設けられたダイオード部と
を備え、
前記ダイオード部は、
少なくとも一部が前記半導体基板の上面に露出する第2導電型のアノード領域と、
前記アノード領域の下方に設けられた第1導電型のドリフト領域と、
前記ドリフト領域の下方に設けられた第1導電型のカソード領域と、
前記アノード領域を少なくとも貫通して、予め定められた配列方向に沿って配列された複数のダミートレンチ部と、
前記配列方向とは異なる複数のダミートレンチ部の延伸方向に沿って設けられたコンタクト部と、
前記ドリフト領域の下方に設けられ、前記延伸方向における前記コンタクト部の外側の端部の直下に設けられる第2導電型の下面側半導体領域と、
前記アノード領域と前記ドリフト領域との間とに設けられ、前記ドリフト領域よりも高い第1導電型のドーピング濃度を有する第1導電型の蓄積領域と、
を有し、
前記蓄積領域の前記延伸方向における外側の端部は、前記コンタクト部の前記延伸方向における外側の端部よりも内側に設けられ、
前記下面側半導体領域は、少なくとも前記コンタクト部の前記延伸方向における外側の端部の直下から前記蓄積領域の前記延伸方向の端部の直下よりも外側まで連続して設けられる、半導体装置。 - 半導体基板と、
前記半導体基板に設けられたトランジスタ部と、
前記トランジスタ部に隣接して、前記半導体基板に設けられたダイオード部と
を備え、
前記ダイオード部は、
少なくとも一部が前記半導体基板の上面に露出する第2導電型のアノード領域と、
前記アノード領域の下方に設けられた第1導電型のドリフト領域と、
前記ドリフト領域の下方に設けられた第1導電型のカソード領域と、
前記アノード領域を少なくとも貫通して、予め定められた配列方向に沿って配列された複数のダミートレンチ部と、
前記配列方向とは異なる複数のダミートレンチ部の延伸方向に沿って設けられたコンタクト部と、
前記ドリフト領域の下方に設けられ、前記延伸方向における前記コンタクト部の外側の端部の直下に設けられる第2導電型の下面側半導体領域と、
前記アノード領域と前記ドリフト領域との間とに設けられ、前記ドリフト領域よりも高い第1導電型のドーピング濃度を有する第1導電型の蓄積領域と、
を有し、
前記延伸方向における前記蓄積領域の端部領域は、外側ほど浅い位置に設けられる、半導体装置。 - 前記トランジスタ部は、
前記半導体基板の上面に露出する第1導電型のエミッタ領域と、
少なくとも一部が前記エミッタ領域の下方に設けられた第2導電型のベース領域と、
前記ベース領域の下方に設けられた第1導電型のドリフト領域と、
前記ベース領域を少なくとも貫通して、前記延伸方向に延伸する複数のゲートトレンチ部と、
前記ベース領域と前記ドリフト領域との間に設けられ、前記ドリフト領域よりも高い第1導電型のドーピング濃度を有する第1導電型の蓄積領域と、
前記ドリフト領域の下方に設けられ、前記ダイオード部における前記蓄積領域の前記延伸方向の外側の端部における直下にも設けられる、前記下面側半導体領域と
を有する、請求項1から6のいずれか一項に記載の半導体装置。 - 前記延伸方向における前記下面側半導体領域の端部から、前記蓄積領域の前記延伸方向における外側の端部までの長さは、
前記蓄積領域の前記延伸方向における外側の端部から、前記コンタクト部の前記延伸方向における外側の端部までの長さよりも長い
請求項4に記載の半導体装置。 - 前記延伸方向における前記下面側半導体領域の端部から、前記蓄積領域の前記延伸方向における外側の端部までの長さは、
前記蓄積領域の前記延伸方向における外側の端部から、前記コンタクト部の前記延伸方向における外側の端部までの長さよりも短い
請求項4に記載の半導体装置。 - 前記下面側半導体領域は、前記蓄積領域の前記延伸方向における外側の端部よりも200μm以上内側まで連続して設けられる
請求項4から9のいずれか一項に記載の半導体装置。 - 前記ダイオード部は、前記複数のダミートレンチ部の間に、前記アノード領域よりも高い第2導電型のドーピング濃度を有する高濃度第2導電型領域と、前記ドリフト領域よりも高い第1導電型のドーピング濃度を有する高濃度第1導電型領域とを有する
請求項1から10のいずれか一項に記載の半導体装置。 - 前記高濃度第1導電型領域および前記高濃度第2導電型領域は、前記延伸方向に延伸し、前記配列方向において互いに隣接する
請求項11に記載の半導体装置。 - 前記高濃度第1導電型領域および前記高濃度第2導電型領域は、前記配列方向に延伸し、前記延伸方向において互いに隣接する
請求項11に記載の半導体装置。 - 前記トランジスタ部は、複数のゲートトレンチ部を有し、
前記複数のゲートトレンチ部は、
前記延伸方向に沿って延伸する第1部分と、
前記配列方向に延伸し、複数の前記第1部分の前記延伸方向の端部に接続する第2部分と、を有する
請求項1から13のいずれか一項に記載の半導体装置。 - 前記第2部分は、3つ以上の前記第1部分の前記延伸方向の端部に接続する
請求項14に記載の半導体装置。 - 前記ダイオード部の前記複数のダミートレンチ部は、
前記延伸方向に沿って延伸する第1部分と、
前記配列方向に延伸し、複数の前記第1部分の前記延伸方向の端部に接続する第2部分と、を有する
請求項14に記載の半導体装置。 - 前記ダミートレンチ部の前記第2部分は、3つ以上の前記ダミートレンチ部の前記第1部分の前記延伸方向の端部に接続する
請求項16に記載の半導体装置。 - 前記複数のゲートトレンチ部の第1部分と前記複数のダミートレンチ部の第1部分とは互いに平行である請求項16に記載の半導体装置。
- 半導体基板と、
前記半導体基板に設けられたトランジスタ部と、
前記トランジスタ部に隣接して、前記半導体基板に設けられたダイオード部と
を備え、
前記ダイオード部は、
少なくとも一部が前記半導体基板の上面に露出する第2導電型のアノード領域と、
前記アノード領域の下方に設けられた第1導電型のドリフト領域と、
前記ドリフト領域の下方に設けられた第1導電型のカソード領域と、
前記アノード領域を少なくとも貫通して、予め定められた配列方向に沿って配列された複数のダミートレンチ部と、
前記配列方向とは異なる複数のダミートレンチ部の延伸方向に沿って設けられたコンタクト部と、
前記ドリフト領域の下方に設けられ、前記延伸方向における前記コンタクト部の外側の端部の直下に設けられる第2導電型の下面側半導体領域と、
を有し、
前記トランジスタ部は、複数のゲートトレンチ部を有し、
前記複数のゲートトレンチ部は、
前記延伸方向に沿って延伸する第1部分と、
前記配列方向に延伸し、複数の前記第1部分の前記延伸方向の端部に接続する第2部分と、を有し、
前記ダイオード部の前記複数のダミートレンチ部は、
前記延伸方向に沿って延伸する第1部分と、
前記配列方向に延伸し、複数の前記第1部分の前記延伸方向の端部に接続する第2部分と、を有し、
前記複数のゲートトレンチ部の第1部分と前記複数のダミートレンチ部の第1部分とは互いに直交する半導体装置。 - 前記ダイオード部はライフタイムキラー領域を備える
請求項16から19のいずれか一項に記載の半導体装置。 - 前記ライフタイムキラー領域は、前記複数のダミートレンチ部の第1部分よりも前記ダイオード部の外側に延伸する
請求項20に記載の半導体装置。 - 前記ライフタイムキラー領域は、前記複数のダミートレンチ部の第2部分よりも前記ダイオード部の外側に延伸する
請求項20に記載の半導体装置。 - 前記ライフタイムキラー領域は、前記複数のゲートトレンチ部の第2部分より外側に延伸する
請求項20に記載の半導体装置。 - 前記複数のゲートトレンチ部の各々は、ゲート絶縁膜に接して、前記ゲート絶縁膜よりも前記複数のゲートトレンチ部の各々の内側に設けられたゲート導電部を有し、
前記半導体装置は、前記半導体基板の上面視で前記トランジスタ部または前記ダイオード部の外側に設けられ且つ前記ゲート導電部と電気的に接続するゲート金属層をさらに備え、
前記ライフタイムキラー領域は、前記ゲート金属層の外側に延伸する
請求項22に記載の半導体装置。 - 前記半導体基板の上面から前記ライフタイムキラー領域までの深さは、前記ライフタイムキラー領域から前記半導体基板の下面までの深さよりも小さい
請求項20に記載の半導体装置。
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