JP6741529B2 - チップ間隔維持方法 - Google Patents
チップ間隔維持方法 Download PDFInfo
- Publication number
- JP6741529B2 JP6741529B2 JP2016176352A JP2016176352A JP6741529B2 JP 6741529 B2 JP6741529 B2 JP 6741529B2 JP 2016176352 A JP2016176352 A JP 2016176352A JP 2016176352 A JP2016176352 A JP 2016176352A JP 6741529 B2 JP6741529 B2 JP 6741529B2
- Authority
- JP
- Japan
- Prior art keywords
- workpiece
- sheet
- chips
- expand
- suction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016176352A JP6741529B2 (ja) | 2016-09-09 | 2016-09-09 | チップ間隔維持方法 |
TW106126221A TWI718326B (zh) | 2016-09-09 | 2017-08-03 | 晶片間隔維持方法 |
CN201710769571.5A CN107808847B (zh) | 2016-09-09 | 2017-08-31 | 芯片间隔维持方法 |
KR1020170112608A KR102305385B1 (ko) | 2016-09-09 | 2017-09-04 | 칩 간격 유지 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016176352A JP6741529B2 (ja) | 2016-09-09 | 2016-09-09 | チップ間隔維持方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018041894A JP2018041894A (ja) | 2018-03-15 |
JP6741529B2 true JP6741529B2 (ja) | 2020-08-19 |
Family
ID=61569821
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016176352A Active JP6741529B2 (ja) | 2016-09-09 | 2016-09-09 | チップ間隔維持方法 |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP6741529B2 (ko) |
KR (1) | KR102305385B1 (ko) |
CN (1) | CN107808847B (ko) |
TW (1) | TWI718326B (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20220145761A (ko) | 2021-04-22 | 2022-10-31 | 가부시기가이샤 디스코 | 칩 간격 형성 방법 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7154809B2 (ja) * | 2018-04-20 | 2022-10-18 | 株式会社ディスコ | ウエーハの加工方法 |
JP2020102569A (ja) * | 2018-12-25 | 2020-07-02 | 東レエンジニアリング株式会社 | 保持テーブル |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6312800B1 (en) * | 1997-02-10 | 2001-11-06 | Lintec Corporation | Pressure sensitive adhesive sheet for producing a chip |
JP4471627B2 (ja) * | 2003-11-06 | 2010-06-02 | 株式会社ディスコ | ウエーハの分割方法 |
JP2006203133A (ja) * | 2005-01-24 | 2006-08-03 | Lintec Corp | チップ体の製造方法、デバイスの製造方法およびチップ体固着用粘接着シート |
JP4754278B2 (ja) * | 2005-06-23 | 2011-08-24 | リンテック株式会社 | チップ体の製造方法 |
JP5378780B2 (ja) | 2008-12-19 | 2013-12-25 | 株式会社ディスコ | テープ拡張方法およびテープ拡張装置 |
JP5313036B2 (ja) * | 2009-05-11 | 2013-10-09 | 株式会社ディスコ | 粘着テープの拡張方法 |
JP5536555B2 (ja) * | 2010-06-22 | 2014-07-02 | 株式会社ディスコ | 拡張テープ収縮装置 |
JP5013148B1 (ja) * | 2011-02-16 | 2012-08-29 | 株式会社東京精密 | ワーク分割装置及びワーク分割方法 |
JP6249586B2 (ja) * | 2011-08-31 | 2017-12-20 | 株式会社東京精密 | ワーク分割装置及びワーク分割方法 |
JP6298635B2 (ja) * | 2014-01-10 | 2018-03-20 | 株式会社ディスコ | 分割装置及び被加工物の分割方法 |
JP2015204362A (ja) * | 2014-04-14 | 2015-11-16 | 株式会社ディスコ | チップ間隔維持方法 |
JP6266429B2 (ja) * | 2014-05-08 | 2018-01-24 | 株式会社ディスコ | チップ間隔維持装置及びチップ間隔維持方法 |
-
2016
- 2016-09-09 JP JP2016176352A patent/JP6741529B2/ja active Active
-
2017
- 2017-08-03 TW TW106126221A patent/TWI718326B/zh active
- 2017-08-31 CN CN201710769571.5A patent/CN107808847B/zh active Active
- 2017-09-04 KR KR1020170112608A patent/KR102305385B1/ko active IP Right Grant
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20220145761A (ko) | 2021-04-22 | 2022-10-31 | 가부시기가이샤 디스코 | 칩 간격 형성 방법 |
Also Published As
Publication number | Publication date |
---|---|
TW201812882A (zh) | 2018-04-01 |
KR102305385B1 (ko) | 2021-09-24 |
CN107808847A (zh) | 2018-03-16 |
JP2018041894A (ja) | 2018-03-15 |
CN107808847B (zh) | 2023-04-11 |
KR20180028932A (ko) | 2018-03-19 |
TWI718326B (zh) | 2021-02-11 |
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