CN107808847B - 芯片间隔维持方法 - Google Patents

芯片间隔维持方法 Download PDF

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Publication number
CN107808847B
CN107808847B CN201710769571.5A CN201710769571A CN107808847B CN 107808847 B CN107808847 B CN 107808847B CN 201710769571 A CN201710769571 A CN 201710769571A CN 107808847 B CN107808847 B CN 107808847B
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CN
China
Prior art keywords
workpiece
sheet
chips
chip
peripheral edge
Prior art date
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Application number
CN201710769571.5A
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English (en)
Chinese (zh)
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CN107808847A (zh
Inventor
原田成规
赵金艳
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Disco Corp
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Disco Corp
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Publication date
Application filed by Disco Corp filed Critical Disco Corp
Publication of CN107808847A publication Critical patent/CN107808847A/zh
Application granted granted Critical
Publication of CN107808847B publication Critical patent/CN107808847B/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
CN201710769571.5A 2016-09-09 2017-08-31 芯片间隔维持方法 Active CN107808847B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016176352A JP6741529B2 (ja) 2016-09-09 2016-09-09 チップ間隔維持方法
JP2016-176352 2016-09-09

Publications (2)

Publication Number Publication Date
CN107808847A CN107808847A (zh) 2018-03-16
CN107808847B true CN107808847B (zh) 2023-04-11

Family

ID=61569821

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710769571.5A Active CN107808847B (zh) 2016-09-09 2017-08-31 芯片间隔维持方法

Country Status (4)

Country Link
JP (1) JP6741529B2 (ko)
KR (1) KR102305385B1 (ko)
CN (1) CN107808847B (ko)
TW (1) TWI718326B (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7154809B2 (ja) * 2018-04-20 2022-10-18 株式会社ディスコ ウエーハの加工方法
JP2020102569A (ja) * 2018-12-25 2020-07-02 東レエンジニアリング株式会社 保持テーブル
JP2022167030A (ja) 2021-04-22 2022-11-04 株式会社ディスコ チップ間隔形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007005530A (ja) * 2005-06-23 2007-01-11 Lintec Corp チップ体の製造方法
CN101887841A (zh) * 2009-05-11 2010-11-17 株式会社迪思科 粘接带的扩展方法
CN104979261A (zh) * 2014-04-14 2015-10-14 株式会社迪思科 芯片间隔维持方法
CN105097479A (zh) * 2014-05-08 2015-11-25 株式会社迪思科 芯片间隔维持装置以及芯片间隔维持方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6312800B1 (en) * 1997-02-10 2001-11-06 Lintec Corporation Pressure sensitive adhesive sheet for producing a chip
JP4471627B2 (ja) * 2003-11-06 2010-06-02 株式会社ディスコ ウエーハの分割方法
JP2006203133A (ja) * 2005-01-24 2006-08-03 Lintec Corp チップ体の製造方法、デバイスの製造方法およびチップ体固着用粘接着シート
JP5378780B2 (ja) 2008-12-19 2013-12-25 株式会社ディスコ テープ拡張方法およびテープ拡張装置
JP5536555B2 (ja) * 2010-06-22 2014-07-02 株式会社ディスコ 拡張テープ収縮装置
JP5013148B1 (ja) * 2011-02-16 2012-08-29 株式会社東京精密 ワーク分割装置及びワーク分割方法
JP6249586B2 (ja) * 2011-08-31 2017-12-20 株式会社東京精密 ワーク分割装置及びワーク分割方法
JP6298635B2 (ja) * 2014-01-10 2018-03-20 株式会社ディスコ 分割装置及び被加工物の分割方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007005530A (ja) * 2005-06-23 2007-01-11 Lintec Corp チップ体の製造方法
CN101887841A (zh) * 2009-05-11 2010-11-17 株式会社迪思科 粘接带的扩展方法
CN104979261A (zh) * 2014-04-14 2015-10-14 株式会社迪思科 芯片间隔维持方法
CN105097479A (zh) * 2014-05-08 2015-11-25 株式会社迪思科 芯片间隔维持装置以及芯片间隔维持方法

Also Published As

Publication number Publication date
JP6741529B2 (ja) 2020-08-19
TW201812882A (zh) 2018-04-01
KR102305385B1 (ko) 2021-09-24
CN107808847A (zh) 2018-03-16
JP2018041894A (ja) 2018-03-15
KR20180028932A (ko) 2018-03-19
TWI718326B (zh) 2021-02-11

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