JP6399228B2 - 半導体装置 - Google Patents
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- JP6399228B2 JP6399228B2 JP2017535185A JP2017535185A JP6399228B2 JP 6399228 B2 JP6399228 B2 JP 6399228B2 JP 2017535185 A JP2017535185 A JP 2017535185A JP 2017535185 A JP2017535185 A JP 2017535185A JP 6399228 B2 JP6399228 B2 JP 6399228B2
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- 239000004065 semiconductor Substances 0.000 title claims description 45
- 239000010410 layer Substances 0.000 claims description 101
- 239000000758 substrate Substances 0.000 claims description 64
- 238000009792 diffusion process Methods 0.000 claims description 30
- 239000012535 impurity Substances 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 2
- 230000004048 modification Effects 0.000 description 14
- 238000012986 modification Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 5
- 230000000593 degrading effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
図1は、本発明の実施の形態1に係る半導体装置を示す斜視図である。図2は、本発明の実施の形態1に係る半導体装置を示す断面図である。図3は、本発明の実施の形態1に係る半導体装置の基板を示す上面図である。この半導体装置は、CSTBT(Carrier Stored Trench Gate Bipolar Transistor)構造のIGBT(Insulated Gate Bipolar Transistor)である。
図8は、本発明の実施の形態2に係る半導体装置を示す斜視図である。図9は、本発明の実施の形態2に係る半導体装置の基板を示す上面図である。本実施の形態では、実施の形態1の第3のダミートレンチ11の代わりに、ダミーセル領域のp型ベース層3及びp+型コンタクト層4の不純物濃度をアクティブセル領域のp型ベース層3及びp+型コンタクト層4よりも低くする。その他の構成は実施の形態1と同様である。
図11は、本発明の実施の形態3に係る半導体装置を示す斜視図である。図12は、本発明の実施の形態3に係る半導体装置の基板を示す下面図である。本実施の形態では、実施の形態1の第3のダミートレンチ11の代わりに、p型コレクタ層として、アクティブセル領域と基板中央部のダミーセル領域に設けられた第1のp型コレクタ層17aと、基板端部のダミーセル領域に設けられ第1のp型コレクタ層17aよりも高い不純物濃度を持つ第2のp型コレクタ層17bとを設けている。第2のp型コレクタ層17bはp型ウェル層15直下に限定されず、基板中央部に向かって不純物濃度が徐々に下がっていくフローティング構造を有する。
Claims (2)
- アクティブセル領域とダミーセル領域を有するn型基板と、
前記n型基板の上面側に設けられたp型拡散層と、
前記アクティブセル領域において前記p型拡散層上の一部に設けられたn型エミッタ層と、
前記アクティブセル領域において前記p型拡散層と前記n型エミッタ層を貫通するゲートトレンチと、
前記ダミーセル領域において前記p型拡散層を貫通し、平面視で前記ゲートトレンチに平行に設けられた第1及び第2のダミートレンチと、
前記n型エミッタ層、前記アクティブセル領域の前記p型拡散層、及び基板端部の前記ダミーセル領域の前記p型拡散層に接続されたエミッタ電極と、
前記第1及び第2のダミートレンチで挟まれた基板中央部の前記p型拡散層を前記エミッタ電極から絶縁させる層間絶縁膜と、
前記n型基板の下面側に設けられたp型コレクタ層と、
前記p型コレクタ層に接続されたコレクタ電極とを備え、
前記p型コレクタ層は、前記アクティブセル領域と前記基板中央部の前記ダミーセル領域に設けられた第1のp型コレクタ層と、前記基板端部の前記ダミーセル領域に設けられ前記第1のp型コレクタ層よりも高い不純物濃度を持つ第2のp型コレクタ層とを有することを特徴とする半導体装置。 - 前記第2のp型コレクタ層は前記基板中央部に向かって不純物濃度が徐々に下がっていくフローティング構造を有することを特徴とする請求項1に記載の半導体装置。
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PCT/JP2015/073209 WO2017029719A1 (ja) | 2015-08-19 | 2015-08-19 | 半導体装置 |
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JPWO2017029719A1 JPWO2017029719A1 (ja) | 2017-11-30 |
JP6399228B2 true JP6399228B2 (ja) | 2018-10-03 |
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US (1) | US10355082B2 (ja) |
JP (1) | JP6399228B2 (ja) |
CN (1) | CN107924940B (ja) |
DE (1) | DE112015006812B4 (ja) |
WO (1) | WO2017029719A1 (ja) |
Families Citing this family (7)
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CN105226090B (zh) * | 2015-11-10 | 2018-07-13 | 株洲中车时代电气股份有限公司 | 一种绝缘栅双极晶体管及其制作方法 |
US10636877B2 (en) * | 2016-10-17 | 2020-04-28 | Fuji Electric Co., Ltd. | Semiconductor device |
DE102018112344A1 (de) | 2017-05-29 | 2018-11-29 | Infineon Technologies Ag | Leistungshalbleitervorrichtung mit dV/dt-Steuerbarkeit und Quergrabenanordnung |
DE102018130095B4 (de) | 2018-11-28 | 2021-10-28 | Infineon Technologies Dresden GmbH & Co. KG | Halbleiterleistungsschalter mit verbesserter Steuerbarkeit |
CN109755300B (zh) * | 2018-11-28 | 2020-11-10 | 株洲中车时代半导体有限公司 | 一种沟槽igbt芯片 |
US11004969B2 (en) * | 2019-10-07 | 2021-05-11 | Nami MOS CO., LTD. | Trench MOSFETs having dummy cells for avalanche capability improvement |
JP7438080B2 (ja) * | 2020-10-30 | 2024-02-26 | 三菱電機株式会社 | 半導体装置 |
Family Cites Families (16)
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JP3410913B2 (ja) | 1996-11-29 | 2003-05-26 | 株式会社東芝 | 電力用半導体装置 |
EP1089343A3 (en) | 1999-09-30 | 2003-12-17 | Kabushiki Kaisha Toshiba | Semiconductor device with trench gate |
JP3971327B2 (ja) * | 2003-03-11 | 2007-09-05 | 株式会社東芝 | 絶縁ゲート型半導体装置 |
JP3906181B2 (ja) * | 2003-05-26 | 2007-04-18 | 株式会社東芝 | 電力用半導体装置 |
JP2009188290A (ja) | 2008-02-08 | 2009-08-20 | Toshiba Corp | 電力用半導体装置 |
JP4688901B2 (ja) | 2008-05-13 | 2011-05-25 | 三菱電機株式会社 | 半導体装置 |
US8304829B2 (en) * | 2008-12-08 | 2012-11-06 | Fairchild Semiconductor Corporation | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
CN102792448B (zh) * | 2010-03-09 | 2015-09-09 | 富士电机株式会社 | 半导体器件 |
JP5287835B2 (ja) * | 2010-04-22 | 2013-09-11 | 株式会社デンソー | 半導体装置 |
JP6037499B2 (ja) * | 2011-06-08 | 2016-12-07 | ローム株式会社 | 半導体装置およびその製造方法 |
WO2013005304A1 (ja) * | 2011-07-05 | 2013-01-10 | 三菱電機株式会社 | 半導体装置 |
JP2014132620A (ja) * | 2013-01-07 | 2014-07-17 | Mitsubishi Electric Corp | 半導体装置 |
JP2015023118A (ja) * | 2013-07-18 | 2015-02-02 | 株式会社東芝 | 半導体装置 |
JP2015162610A (ja) | 2014-02-27 | 2015-09-07 | 株式会社東芝 | 半導体装置 |
JP6158123B2 (ja) * | 2014-03-14 | 2017-07-05 | 株式会社東芝 | 半導体装置 |
JP6253769B2 (ja) * | 2014-04-21 | 2017-12-27 | 三菱電機株式会社 | 電力用半導体装置 |
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2015
- 2015-08-19 CN CN201580082520.4A patent/CN107924940B/zh active Active
- 2015-08-19 US US15/570,442 patent/US10355082B2/en active Active
- 2015-08-19 DE DE112015006812.0T patent/DE112015006812B4/de active Active
- 2015-08-19 JP JP2017535185A patent/JP6399228B2/ja active Active
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WO2017029719A1 (ja) | 2017-02-23 |
US20180083101A1 (en) | 2018-03-22 |
JPWO2017029719A1 (ja) | 2017-11-30 |
DE112015006812B4 (de) | 2024-02-22 |
CN107924940A (zh) | 2018-04-17 |
CN107924940B (zh) | 2021-02-05 |
US10355082B2 (en) | 2019-07-16 |
DE112015006812T5 (de) | 2018-04-26 |
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Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |