JP6304243B2 - 半導体装置、半導体装置の製造方法 - Google Patents
半導体装置、半導体装置の製造方法 Download PDFInfo
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- JP6304243B2 JP6304243B2 JP2015511072A JP2015511072A JP6304243B2 JP 6304243 B2 JP6304243 B2 JP 6304243B2 JP 2015511072 A JP2015511072 A JP 2015511072A JP 2015511072 A JP2015511072 A JP 2015511072A JP 6304243 B2 JP6304243 B2 JP 6304243B2
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- adhesive
- dicing
- semiconductor device
- wafer
- surface roughness
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- 238000000034 method Methods 0.000 title claims description 39
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000853 adhesive Substances 0.000 claims description 53
- 230000001070 adhesive effect Effects 0.000 claims description 52
- 230000003746 surface roughness Effects 0.000 claims description 33
- 239000000155 melt Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 32
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Description
図1は、本発明の実施の形態1に係る半導体装置の断面図である。半導体装置10は実装基板12を備えている。実装基板12には接着剤14が塗布されている。接着剤14により実装基板12とデバイス16の下面が接着している。デバイス16は例えばGaAsなどの化合物半導体で形成されている。デバイス16の上面は電極パッド18が形成された能動領域となっている。
本発明の実施の形態2に係る半導体装置と半導体装置の製造方法は、実施の形態1との共通点が多いので実施の形態1との相違点を中心に説明する。図7は、本発明の実施の形態2に係る半導体装置の断面図である。この半導体装置は接着剤14によりデバイス200の下面が実装基板12に固定されたものである。
Claims (4)
- 実装基板と、
前記実装基板に塗布された接着剤と、
前記接着剤により下面が前記実装基板と接着されたデバイスと、を備え、
前記デバイスの側面上部は前記デバイスの多孔質で構成された側面下部より表面粗さが小さく、
前記デバイスの側面は平坦であることを特徴とする半導体装置。 - 前記デバイスの側面上部には表面粗さRzが1.0μm以下のダイシング痕が形成され、
前記デバイスの側面下部には表面粗さRzが4.0μm以上のダイシング痕が形成されたことを特徴とする請求項1に記載の半導体装置。 - 前記接着剤の一部は前記側面下部を覆うことを特徴とする請求項1又は2に記載の半導体装置。
- レーザダイシングによりウエハに貫通孔を形成し個々のデバイスに分離するレーザダイシング工程と、
前記レーザダイシング工程で前記デバイスの側面に形成された溶融物をブレード又はエッチングにより除去する除去工程と、
前記除去工程の後に、接着剤により実装基板と前記デバイスの下面とを接着するダイボンド工程と、
前記接着剤を硬化させる接着剤硬化工程と、を備え、
前記除去工程では、前記デバイスの側面上部に形成された溶融物のみを除去することで、前記デバイスの側面上部は前記デバイスの側面下部より表面粗さが小さく、前記デバイスの側面は平坦となることを特徴とする半導体装置の製造方法。
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US (1) | US11233029B2 (ja) |
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DE102019124181B4 (de) * | 2018-09-28 | 2023-06-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vereinzelungsverfahren für gestapelte Halbleiter-Bauelemente sowie gestapelte Halbleitervorrichtung |
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- 2013-10-15 EP EP13881860.4A patent/EP2985785B1/en active Active
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EP2985785A4 (en) | 2017-01-11 |
KR20150119350A (ko) | 2015-10-23 |
JPWO2014167745A1 (ja) | 2017-02-16 |
CN105103278A (zh) | 2015-11-25 |
EP2985785B1 (en) | 2023-12-20 |
KR101823851B1 (ko) | 2018-01-30 |
CN105103278B (zh) | 2018-11-27 |
KR20170127041A (ko) | 2017-11-20 |
US20150371966A1 (en) | 2015-12-24 |
TWI511239B (zh) | 2015-12-01 |
US11233029B2 (en) | 2022-01-25 |
EP2985785A1 (en) | 2016-02-17 |
TW201440179A (zh) | 2014-10-16 |
WO2014167745A1 (ja) | 2014-10-16 |
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