JP6098514B2 - 双方向素子、双方向素子回路および電力変換装置 - Google Patents
双方向素子、双方向素子回路および電力変換装置 Download PDFInfo
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Description
非特許文献1 H.Takahashi, et al., "1200V class Reverse Blocking IGBT (RB-IGBT) for AC Matrix Converter", Proceedings of 2004 International Symposium on Power Semiconductor Devices & ICs, Kitakyushu, p.121
非特許文献2 T.Naito, et al., "1200V Reverse Blocking IGBT with low loss for Matrix Converter", Proceedings of 2004 International Symposium on Power Semiconductor Devices & ICs, Kitakyushu, p.125
特許文献1 特開2002−319676号公報
特許文献2 特開平3−194971号公報
1)シリコン基板に形成した逆阻止IGBTは、要求される耐圧が高くなるにつれシリコン基板を厚くしなければならず、結果としてシリコン基板の抵抗が大きくなり、全体の効率が低下する。また、シリコン基板を厚くするとデバイスサイズも大きくなるので実用的でない。
2)逆阻止IGBTの半導体基板を炭化ケイ素(SiC)または窒化ガリウム(GaN)などのワイドバンドギャップ材料により形成した場合、PN接合のビルトイン電圧がシリコンより大きいため、IGBTの順方向電圧が大きく設定される。
3)逆阻止IGBTにおいては、制御電極に正電圧を印加し続けるとフライホイーリングダイオードとして動作する。したがって、IGBTとしての最適なデバイス構造とダイオードとしての最適なデバイス構造を単一のデバイスで実現するのが好ましい。しかしながら、IGBT動作時に順方向に耐圧が印加された場合、空乏層をコレクタ側で止めるためのフィールドストップ層を設けることができず、ベース層を厚くすることにより対処しなければならない。その結果、ドリフト層が厚くなり、抵抗が高くなってスイッチング特性やオン電圧特性が通常のデバイスに比べ低下する。
4)逆阻止IGBTを用いた場合でも双方向スイッチを構成するためには2個のパワーデバイスが必要となる。
Claims (18)
- 基板の表面に形成された半導体積層部の積層方向に電流が流れる縦型の双方向素子であって、
前記半導体積層部に形成され、第1チャネルを有する第1半導体素子と、
前記半導体積層部において前記第1半導体素子よりも前記基板側に設けられ、第2チャネルを有する第2半導体素子と
を備え、
前記第1半導体素子は、前記半導体積層部の面のうち前記基板とは逆側の面に形成され、且つ、前記第1チャネルを制御する第1制御電極を更に有し、
前記第2半導体素子は、前記半導体積層部の面のうち前記第1制御電極と同じ側の面に少なくとも一部が形成され、且つ、前記第2チャネルを制御する第2制御電極と
を有し、
前記半導体積層部は、
前記第1チャネルよりも前記基板側に形成された、第1導電型の半導体層と、
前記第1導電型の半導体層内の前記基板と略平行な面において、前記第1導電型の半導体層の一部の領域を残して形成された第2導電型の第1半導体領域と
を有し、
前記第1半導体領域が形成される面に残された前記第1導電型の半導体層に前記第2チャネルが形成され、
前記第1導電型の半導体層は、
前記基板上に形成された高濃度層と、
前記高濃度層上に形成され、前記高濃度層よりも不純物濃度が低い低濃度層と、
を有し、
前記半導体積層部は、
前記第1半導体領域よりも前記第1制御電極側における前記基板と略平行な面において、前記低濃度層である第1導電型の第2半導体領域と、第2導電型の第3半導体領域と、第1導電型の第4半導体領域とを順番に隣接して有し、
前記第1チャネルは、前記第2導電型の第3半導体領域に形成され、
前記第1半導体領域は、前記高濃度層および前記低濃度層との境界に形成され、
前記第2制御電極は、前記第1半導体領域に接し、
前記第2制御電極は、前記低濃度層によって前記第3半導体領域および前記第1制御電極と分離されつつ、前記高濃度層に接し、
前記第2制御電極は前記第1半導体素子および前記第1半導体領域を取り囲む
双方向素子。 - 前記第1半導体領域は、前記第1導電型の半導体層が前記基板と略平行な面において離散して複数存在するように形成される
請求項1に記載の双方向素子。 - 前記第1半導体領域が形成される面において、前記第1導電型の半導体層は、略一定の間隔で配置される
請求項2に記載の双方向素子。 - 前記第2半導体領域、前記第3半導体領域および前記第4半導体領域は、前記低濃度層の表面に形成される
請求項1に記載の双方向素子。 - 前記第2チャネルは、前記高濃度層および前記低濃度層の境界部分に形成され、前記基板と略垂直な方向にキャリアが移動するチャネルである
請求項4に記載の双方向素子。 - 前記第2制御電極は、前記半導体積層部の表面から前記第1半導体領域まで、前記第1導電型の半導体層内を通って形成される
請求項1から5のいずれか一項に記載の双方向素子。 - 前記第2制御電極が、前記第1半導体領域とオーミック接合し、かつ、前記第1導電型の半導体層とショットキー接合する材料で形成される
請求項6に記載の双方向素子。 - 前記第2制御電極が、前記第1半導体領域とオーミック接合する材料で形成され、
前記半導体積層部は、前記第1導電型の半導体層と前記第2制御電極との間に設けられた絶縁膜を更に有する
請求項6に記載の双方向素子。 - 前記第2制御電極が前記第1半導体領域とオーミック接合する材料で形成され、
前記半導体積層部は、前記第1導電型の半導体層と前記第2制御電極との間に設けられた、第2導電型の第5半導体領域を更に有する
請求項6に記載の双方向素子。 - 前記半導体積層部は、前記第1半導体領域から前記半導体積層部の表面まで形成された、第2導電型の第6半導体領域を更に有し、
前記第2制御電極は、前記第6半導体領域とオーミック接合する
請求項1から5のいずれか一項に記載の双方向素子。 - 前記第1導電型はn型であり、前記第2導電型はp型である
請求項1から10のいずれか一項に記載の双方向素子。 - 前記半導体積層部は、SiCまたは窒化物半導体から形成される層を含む
請求項1から11のいずれか一項に記載の双方向素子。 - 前記半導体積層部の表面に設けられた第1電極と、
前記基板の裏面に設けられた第2電極と、
をさらに備え、
前記第1電極と前記第2半導体領域との間、および、前記第2電極と前記基板の一部に設けられた前記第1導電型の半導体層との間の少なくとも一方にはショットキー接合が形成される、請求項1または4に記載の双方向素子。 - 前記第1半導体領域は、互いに接続された複数の半導体領域を有し、
前記複数の半導体領域は、前記基板と略平行な面において、前記複数の半導体領域のうち互いに隣り合う半導体領域の間に間隔を有し、
前記第2電極と前記第1導電型の半導体層との間に前記ショットキー接合が形成された領域上に位置する前記間隔は、前記ショットキー接合が形成された領域上に位置しない前記間隔よりも大きい
請求項13に記載の双方向素子。 - 請求項1から12のいずれか一項に記載の双方向素子と、
前記双方向素子を制御する制御回路と
を備える双方向素子回路。 - 前記双方向素子は、
前記半導体積層部の表面に形成された第1電極と、
前記基板の裏面に形成された第2電極と
を更に有し、
前記制御回路は、
前記第1電極に正の極性の電圧が印加され、且つ、前記第2電極に負の極性の電圧が印加される場合に、前記第1制御電極および前記第2制御電極の制御を同期して行う請求項15に記載の双方向素子回路。 - 前記制御回路は、前記第1半導体素子に対してノーマリオフの制御を行い、前記第2半導体素子に対してノーマリオンの制御を行う
請求項15または16に記載の双方向素子回路。 - 受け取った交流電力の電力を変換して出力する電力変換装置であって、
前記交流電力を受け取る入力側回路と、
前記交流電力を出力する出力側回路と、
前記入力側回路および前記出力側回路の間に設けられた、請求項1から14のいずれか一項に記載の双方向素子と
を備える電力変換装置。
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