JP5926216B2 - 埋込み層に低抵抗コンタクトを形成する打込み領域を含んだ半導体デバイスの製作方法および関連したデバイス - Google Patents
埋込み層に低抵抗コンタクトを形成する打込み領域を含んだ半導体デバイスの製作方法および関連したデバイス Download PDFInfo
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- JP5926216B2 JP5926216B2 JP2013099518A JP2013099518A JP5926216B2 JP 5926216 B2 JP5926216 B2 JP 5926216B2 JP 2013099518 A JP2013099518 A JP 2013099518A JP 2013099518 A JP2013099518 A JP 2013099518A JP 5926216 B2 JP5926216 B2 JP 5926216B2
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
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Description
Claims (44)
- 半導体デバイスを製作する方法であって、
第1の半導体層を形成するステップと、
前記第1の半導体層の伝導度よりも低い伝導度を有する第2の半導体層を、前記第1の半導体層上に形成するステップと、
少なくとも約5×1020イオン/cm3の打込みドーパント濃度を有する打込みドーパント分布を含む打込み領域を形成するように、前記第2の半導体層中にイオンを打ち込むステップと、
前記第2の半導体層の前記打込み領域上に電極を形成するステップと、
前記打込み領域から間隔をあけて配置された、前記第2の半導体層の非打込み領域上に非オーミックコンタクトを形成するステップと
を含むことを特徴とする方法。 - 前記電極と前記非オーミックコンタクトを形成するステップは、
前記第2の半導体層の前記打込まれた領域と前記非打込み領域の上に導電材を形成し、
前記導電材をパターン化して、前記打込み領域の上に前記電極を、前記非打込み領域の上に前記非オーミックコンタクトを定めるステップを含むことを特徴とする請求項1に記載の方法。 - 前記第2の半導体層の上に保護層をさらに形成し、
前記保護層を貫通して前記第2の半導体層へイオンを打込むステップは、打込まれた領域が、前記第2半導体層全体にわたり、かつ少なくとも部分的に前記保護層中に形成されるように打込むステップを含むことを特徴とする請求項2に記載の方法。 - 前記イオンを打込むステップは、
前記第2の半導体層の打込まれた領域全域に亘り実質的に均一な濃度をもつ前記打込みドーパントの分布を提供し、前記打込みドーパントの分布を前記第2の半導体層を貫通して延ばし、しかし前記第1の半導体層を完全に貫通させずに部分的に入るように、イオンを前記第2の半導体層へ打込むステップを含むことを特徴とする請求項3に記載の方法。 - 前記イオンを打込む前記ステップの後で、前記打込みイオンを活性化するために前記第1および第2の半導体層および前記保護層をアニールするステップをさらに含むことを特徴とする請求項4に記載の方法。
- 前記電極を形成する前記ステップは、前記導電材を形成する前に、さらにアニールする前記ステップの後で、前記第2の半導体層の前記打込み領域を露出させるように前記保護層に開口を形成するステップを含み、
前記導電材は前記開口中の前記露出された打込み領域上に形成されることを特徴とする請求項5に記載の方法。 - 前記第1の半導体層および前記第2の半導体層は、III族窒化物材料を含むことを特徴とする請求項6に記載の方法。
- 前記保護層は、少なくとも700℃の温度でその場で成長した窒化物を含むことを特徴とする請求項7に記載の方法。
- 前記第1および第2の半導体層は、窒化ガリウム(GaN)を含み、前記保護層を形成する前記ステップは、
アルミニウムを含むIII族窒化物を含む第1の保護層を前記第2の半導体層上に形成するステップと、
少なくとも700℃の温度でその場で成長した窒化物を含む第2の保護層を、前記第1の保護層上に形成するステップと
を含むことを特徴とする請求項8に記載の方法。 - 前記第1の半導体層と前記イオンを打込まれた領域は第1の伝導型であり、
実質的に一様な濃度を有する前記打込みドーパントの分布を提供するように前記イオンを前記第2の半導体層中に打ち込む前記ステップは、
第1のドーズ量および第1の打込みエネルギーで前記第1の伝導型のイオンを打ち込むステップと、
次いで、第2のドーズ量および第2の打込みエネルギーで前記第1の伝導型のイオンを打ち込むステップとを含み、
前記第2の打込みエネルギーは前記第1の打込みエネルギーよりも高いことを含む
ことを特徴とする請求項9に記載の方法。 - 前記第1のドーズ量は、約0.5×1015から約2.5×1015イオン/cm2を含み、前記第1の打込みエネルギーは約160keVを含み、前記第2のドーズ量は、約0.8×1015から約5×1015イオン/cm2を含み、前記第2の打込みエネルギーは約260keVを含むことを特徴とする請求項10に記載の方法。
- 実質的に一様な濃度を有する前記打込みドーパントの分布を提供するように前記イオンを前記第2の半導体層中に打ち込む前記ステップは、
前記第1の伝導型のイオンを第3のドーズ量および第3の打込みエネルギーで打ち込むステップをさらに含むことを特徴とする請求項11に記載の方法。 - 前記第3のドーズ量は、約0.5×1015から約3.7×1015イオン/cm2を含み、前記第3の打込みエネルギーは約360keVを含むことを特徴とする請求項12に記載の方法。
- 前記保護層は、窒化珪素(SiN)、二酸化珪素(SiO2)、および/または酸窒化珪素(SiON)を含むことを特徴とする請求項13に記載の方法。
- 前記打込みイオンは、珪素(Si)、硫黄(S)、および/または酸素(O)を含むことを特徴とする請求項14に記載の方法。
- 前記第1の半導体層および前記第2の半導体層は、同じ材料を含むことを特徴とする請求項15に記載の方法。
- 前記第1の半導体層および/または前記第2の半導体層は、エピタキシャル層を含むことを特徴とする請求項16に記載の方法。
- 前記電極は、オーミックコンタクトを含むことを特徴とする請求項17に記載の方法。
- 前記電極は、前記第2の半導体層の前記打込み領域上の陰極コンタクトを含み、
前記非オーミックコンタクトは、前記第2の半導体層の前記非打込み領域上の陽極コンタクトを含むことを特徴とする請求項18に記載の方法。 - 前記第1の半導体層および/または前記第2の半導体層は、約100ナノメートル(nm)から約500nmの厚さを有することを特徴とする請求項19に記載の方法。
- 前記非オーミックコンタクトと前記打込み領域の間の横方向距離は、前記非オーミックコンタクトと前記電極の間の横方向距離よりも小さく、前記非オーミックコンタクトと前記打込み領域の間の前記横方向距離は、約1マイクロメートル(μm)未満であることを特徴とする請求項20に記載の方法。
- 前記電極は、前記第2の半導体層の前記打込み領域上のソース/ドレインコンタクトを含み、前記非オーミックコンタクトは、前記第2の半導体層の前記非打込み領域上のゲートコンタクトを含むことを特徴とする請求項1に記載の方法。
- 前記第2の半導体層のバンドギャップは、前記第1の半導体層のバンドギャップよりも大きいことを特徴とする請求項22に記載の方法。
- 前記打込み領域が前記第2の半導体層中にピークドーパント濃度を有することを特徴とする請求項1に記載の方法。
- 半導体デバイスであって、
第1のドーパント濃度を有する第1の半導体層と、
前記第1のドーパント濃度よりも低い第2のドーパント濃度を有する、前記第1の半導体層上の第2の半導体層と、
少なくとも約5×1020イオン/cm3の打込みドーパント濃度を有する打込みドーパントの分布を含む前記第2の半導体層中の打込み領域と、
前記第2の半導体層の前記打込み領域上の電極と、
前記打込み領域から間隔をあけて配置された、前記第2の半導体層の非打込み領域上の非オーミックコンタクトと
を含むことを特徴とする半導体デバイス。 - 前記第1の半導体層および前記第2の半導体層は、III族窒化物材料を含むことを特徴とする請求項25に記載のデバイス。
- 前記第2の半導体層上に保護層をさらに含み、前記第2の半導体層上の前記保護層は、前記保護層を貫通して延び、前記第2の半導体層の前記打込み領域を露出させる開口を含み、前記電極は、前記保護層の前記開口を通して前記第2の半導体層の前記打込み領域まで延びるオーミックコンタクトを含むことを特徴とする請求項25に記載のデバイス。
- 前記保護層は、窒化珪素(SiN)、二酸化珪素(SiO2)、および/または酸窒化珪素(SiON)を含むことを特徴とする請求項27に記載のデバイス。
- 前記オーミックコンタクトは、前記保護層に直接接触していることを特徴とする請求項27に記載のデバイス。
- 打込みドーパントの前記分布は、少なくとも部分的に前記保護層中に延びていることを特徴とする請求項27に記載のデバイス。
- 前記電極および前記非オーミックコンタクトは、同じ材料層から形成されることを特徴とする請求項25に記載のデバイス。
- 前記第1の半導体層と前記イオンを打込まれた領域は第1の伝導型であり、
前記打込み領域は、約5×1020イオン/cm3のピークドーパント濃度を有することを特徴とする請求項31に記載のデバイス。 - 打込みドーパントの前記分布は、前記第2の半導体層の前記打込み領域全体にわたって実質的に一様な濃度を有し、前記打込みドーパントの分布を前記第2の半導体層を貫通して延ばし、しかし前記第1の半導体層を完全に貫通させずに部分的に入れることを特徴とする請求項25に記載のデバイス。
- 前記打込みドーパントは、珪素(Si)、硫黄(S)、および/または酸素(O)を含むことを特徴とする請求項25に記載のデバイス。
- 前記第1の半導体層および前記第2の半導体層は、同じ材料を含むことを特徴とする請求項26に記載のデバイス。
- 前記電極は、オーミックコンタクトを含むことを特徴とする請求項25に記載のデバイス。
- 前記電極は、前記第2の半導体層の前記打込み領域上の陰極コンタクトを含み、
前記非オーミックコンタクトは、前記第2の半導体層の前記非打込み領域上の陽極コンタクトを含むことを特徴とする請求項25に記載のデバイス。 - 前記第1の半導体層および/または前記第2の半導体層は、約100ナノメートル(nm)から約500nmの厚さを有することを特徴とする請求項37に記載のデバイス。
- 前記非オーミックコンタクトと前記打込み領域の間の横方向距離は、前記非オーミックコンタクトと前記電極の間の横方向距離よりも小さく、前記非オーミックコンタクトと前記打込み領域の間の前記横方向距離は、約1マイクロメートル(μm)未満であることを特徴とする請求項25に記載のデバイス。
- 前記電極は、前記第2の半導体層の前記打込み領域上のソース/ドレインコンタクトを含み、前記非オーミックコンタクトは、前記第2の半導体の前記非打込み領域上のゲートコンタクトを含むことを特徴とする請求項25に記載のデバイス。
- 前記第2の半導体層のバンドギャップは、前記第1の半導体層のバンドギャップよりも大きいことを特徴とする請求項40に記載のデバイス。
- 前記打込み領域が前記第2の半導体層中にピークドーパント濃度を有することを特徴とする請求項25に記載のデバイス。
- 前記イオンを打ち込むステップは、前記打込み領域内の少なくとも約1500オングストロームの深さで、少なくとも約5×1020イオン/cm3の前記打込みドーパント濃度を有する前記打込みドーパント分布を含む前記打込み領域を形成するように、前記第2の半導体層中に前記イオンを打ち込むステップを含む、請求項1に記載の方法。
- 前記第2の半導体層中の前記打込み領域は、前記打込み領域内の少なくとも約1500オングストロームの深さで、少なくとも約5×1020イオン/cm3の前記打込みドーパント濃度を有する前記打込みドーパント分布を含む、請求項25に記載のデバイス。
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