JP5875680B2 - 絶縁ゲート型バイポーラトランジスタ - Google Patents
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Description
図7は、本発明の前提技術に係る逆導通型の絶縁ゲート型バイポーラトランジスタ(SJ−RC−IGBT)の構造を示す断面図である。
本実施の形態のSJ−RC−IGBTの断面図を図1に示す。図1は図7と同一の構成を示しており、本実施の形態に係るSJ−RC−IGBTの構造と基本動作は、前提技術に係るSJ−RC−IGBTと同一の構成であるため、説明は省略する。
出願人は、第1ドリフト層(N−ドリフト層1及びP−ドリフト層2)の繰り返しピッチ、当該繰り返し構造の厚みL1、N−ドリフト層1の不純物濃度、Nバッファ層11の厚み及び不純物濃度、コレクタ層(Pコレクタ層12及びNコレクタ層13)の繰り返しピッチL3を適宜調整してシミュレーションを行った。その結果、N−ドリフト層1及びP−ドリフト層2の不純物濃度を1×1015atms/cm3以上2×1016atms/cm3未満に、その厚みを10μm以上50μm未満に、Nバッファ層11の不純物濃度を1×1015atms/cm3以上2×1016atms/cm3未満に、その厚みを2μm以上15μm未満にすることが望ましいことが分かった。これにより、SJ−RC−IGBTの順方向出力特性において、高い電流密度でもMOSFET動作を行うことが可能になった。
図4は、変形例に係るSJ−RC−IGBTの断面図である。このSJ−RC−IGBTは、N−ドリフト層1、P−ドリフト層2、絶縁層15がこの順で図中の水平方向に繰り返された超接合構造を有しており、その他の構成は図1に示す構造と同様である。このようなSJ−RC−IGBTにおいても、N−ドリフト層1及びP−ドリフト層2の不純物濃度を1×1015atms/cm3以上2×1016atms/cm3未満に、その厚みを10μm以上50μm未満に、Nバッファ層11の不純物濃度を1×1015atms/cm3以上2×1016atms/cm3未満に、その厚みを2μm以上15μm未満にすることにより、従来よりも高い電流密度まで、オン抵抗の小さなMOSFET動作を行うことが出来る。
本発明の絶縁ゲート型バイポーラトランジスタは、第1導電型のNバッファ層11(バッファ層)と、Nバッファ層11の第1主面上に形成された第1ドリフト層と、第1ドリフト層上に形成された第1導電型のNドリフト層3(第2ドリフト層)と、Nドリフト層3上に形成された第2導電型のPベース層4(ベース層)と、Pベース層4表面に選択的に形成された第1導電型のNエミッタ層5(エミッタ層)と、Nエミッタ層5の表面からNドリフト層3中へと貫通して絶縁ゲート膜7を介して埋め込み形成されたゲート電極8と、Nエミッタ層5と導通するエミッタ電極10と、Nバッファ層11の第2主面上に形成されたコレクタ層と、コレクタ層上に形成されたコレクタ電極14とを備えた絶縁ゲート型バイポーラトランジスタである。そして、第1ドリフト層は、第1導電型のN−ドリフト層1(第1の層)と、第2導電型のP−ドリフト層2(第2の層)が水平方向に繰り返された構造であり、コレクタ層(12,13)は、第2導電型の第1コレクタ層(12)と、第1導電型の第2コレクタ層(13)が水平方向に繰り返された構造であり、第1ドリフト層は、不純物濃度が1×1015atms/cm3以上2×1016atms/cm3未満で、且つ厚みが10μm以上50μm未満であり、Nバッファ層11は、不純物濃度が1×1015atms/cm3以上2×1016atms/cm3未満で、且つ厚みが2μm以上15μm未満である。よって、低電流密度において、MOSFETのように順方向電圧降下を小さくすることが可能になる。また、第1ドリフト層の厚みを小さくすることができるため、耐圧を高めることが出来る。また、MOSFET動作を行う電流密度の上限を従来より高めることが出来る。
Claims (7)
- 第1導電型のバッファ層(11)と、
前記バッファ層(11)の第1主面上に形成された第1ドリフト層(1,2)と、
前記第1ドリフト層(1,2)上に形成された第1導電型の第2ドリフト層(3)と、
前記第2ドリフト層(3)上に形成された第2導電型のベース層(4)と、
前記ベース層(4)表面に選択的に形成された第1導電型のエミッタ層(5)と、
前記エミッタ層(5)の表面から前記第2ドリフト層(3)中へと貫通して絶縁ゲート膜(7)を介して埋め込み形成されたゲート電極(8)と、
前記エミッタ層(5)と導通するエミッタ電極(10)と、
前記バッファ層(11)の第2主面上に形成されたコレクタ層(12,13)と、
前記コレクタ層(12,13)上に形成されたコレクタ電極(14)とを備えた絶縁ゲート型バイポーラトランジスタであって、
前記第1ドリフト層(1,2)は、第1導電型の第1の層(1)と、第2導電型の第2の層(2)が水平方向に繰り返された構造であり、
前記コレクタ層(12,13)は、第2導電型の第1コレクタ層(12)と、第1導電型の第2コレクタ層(13)が水平方向に繰り返された構造であり、
前記第1ドリフト層は、不純物濃度が1×1015atms/cm3以上2×1016atms/cm3未満で、且つ厚みが10μm以上50μm未満であり、
前記バッファ層は、不純物濃度が1×1015atms/cm3以上2×1016atms/cm3未満で、且つ厚みが2μm以上15μm未満であり、
前記コレクタ層の繰り返しピッチは、前記第1ドリフト層の繰り返しピッチの5倍以上20000倍未満である、
絶縁ゲート型バイポーラトランジスタ。 - 前記第1ドリフト層において、少なくとも一つの第1の層と当該第1の層の隣の第2の層との間に絶縁層が形成された、
請求項1に記載の絶縁ゲート型バイポーラトランジスタ。 - 第1導電型のバッファ層(11)と、
前記バッファ層(11)の第1主面上に形成された第1ドリフト層(1,2)と、
前記第1ドリフト層(1,2)上に形成された第1導電型の第2ドリフト層(3)と、
前記第2ドリフト層(3)上に形成された第2導電型のベース層(4)と、
前記ベース層(4)表面に選択的に形成された第1導電型のエミッタ層(5)と、
前記エミッタ層(5)の表面から前記第2ドリフト層(3)中へと貫通して絶縁ゲート膜(7)を介して埋め込み形成されたゲート電極(8)と、
前記エミッタ層(5)と導通するエミッタ電極(10)と、
前記バッファ層(11)の第2主面上に形成されたコレクタ層(12,13)と、
前記コレクタ層(12,13)上に形成されたコレクタ電極(14)とを備えた絶縁ゲート型バイポーラトランジスタであって、
前記第1ドリフト層(1,2)は、第1導電型の第1の層(1)、絶縁層、及び第2導電型の第2の層(2)がこの順で水平方向に繰り返された構造であり、
前記コレクタ層(12,13)は、第2導電型の第1コレクタ層(12)と、第1導電型の第2コレクタ層(13)が水平方向に繰り返された構造であり、
前記第1の層および前記第2の層の不純物濃度は1×1015atms/cm3以上2×1016atms/cm3未満であり、
前記第1ドリフト層の厚みは10μm以上50μm未満であり、
前記バッファ層は、不純物濃度が1×1015atms/cm3以上2×1016atms/cm3未満で、且つ厚みが2μm以上15μm未満であり、
前記コレクタ層の繰り返しピッチは、前記第1ドリフト層の繰り返しピッチの5倍以上20000倍未満である、
絶縁ゲート型バイポーラトランジスタ。 - 前記第2ドリフト層と前記ベース層の間に、前記ベース層に接して前記第2ドリフト層よりも不純物濃度の高い、第1導電型のキャリア蓄積層をさらに備える、
請求項1に記載の絶縁ゲート型バイポーラトランジスタ。 - 前記第2ドリフト層と前記ベース層の間に、前記ベース層に接して前記第2ドリフト層よりも不純物濃度の高い、第1導電型のキャリア蓄積層をさらに備える、
請求項3に記載の絶縁ゲート型バイポーラトランジスタ。 - 前記第1コレクタ層の中間点と前記第2コレクタ層との間で、スナップバックピーク電圧時の電流密度において、前記バッファ層に0.5V以上0.7V未満の電圧降下が発生するよう、前記第2導電型のコレクタ層の幅を決定する、
請求項1に記載の絶縁ゲート型バイポーラトランジスタ。 - 前記第1コレクタ層の中間点と前記第2コレクタ層との間で、スナップバックピーク電圧時の電流密度において、前記バッファ層に0.5V以上0.7V未満の電圧降下が発生するよう、前記第2導電型のコレクタ層の幅を決定する、
請求項3に記載の絶縁ゲート型バイポーラトランジスタ。
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