JP5855361B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5855361B2 JP5855361B2 JP2011122135A JP2011122135A JP5855361B2 JP 5855361 B2 JP5855361 B2 JP 5855361B2 JP 2011122135 A JP2011122135 A JP 2011122135A JP 2011122135 A JP2011122135 A JP 2011122135A JP 5855361 B2 JP5855361 B2 JP 5855361B2
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- metal film
- semiconductor device
- film
- surface electrode
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- 239000004065 semiconductor Substances 0.000 title claims description 46
- 229910052751 metal Inorganic materials 0.000 claims description 63
- 239000002184 metal Substances 0.000 claims description 63
- 239000000758 substrate Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 description 13
- 230000035882 stress Effects 0.000 description 12
- 229920001721 polyimide Polymers 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000008646 thermal stress Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
図1は、本発明の実施の形態1に係る半導体装置の断面図である。半導体装置10は、エピタキシャル層12を備えている。エピタキシャル層12の表面側にはベース層14が形成されている。ベース層14を貫くようにポリシリコンゲート16が形成されている。ポリシリコンゲート16はゲート酸化膜18に覆われている。ポリシリコンゲート16はゲート20に接続されている。エピタキシャル層12の裏面側にはコレクタ層22が形成されている。上述の構造全体を基板24と称する。
図2は、本発明の実施の形態2に係る半導体装置の断面図である。実施の形態1の半導体装置と同じ部分は同一符号を付して説明を省略する。
図4は、本発明の実施の形態3に係る半導体装置の平面図である。本発明の実施の形態3に係る半導体装置は、基本的には実施の形態1に係る半導体装置と同一であるが、金属膜の形状と、端部固定膜の重畳部分に特徴がある。
図5Aは、本発明の実施の形態4に係る半導体装置の平面図である。図5Bは、本発明の実施の形態4に係る半導体装置の断面図である。本発明の実施の形態4に係る半導体装置は、基本的には図3を参照して説明した半導体装置と同一であるが、金属膜の形状に特徴がある。
Claims (1)
- 基板と、
前記基板の上に、アルミを含む材料で形成された表面電極と、
前記表面電極の上に、はんだ付け可能な材料で形成された金属膜と、
前記表面電極の上の部分と、前記金属膜の端部の上側に重なる重畳部分とが一体的に形成されて前記金属膜の端部を固定する端部固定膜と、を備え、
前記金属膜は角部を有する形状で形成され、
前記重畳部分は前記金属膜の角部の上だけに形成されたことを特徴とする半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011122135A JP5855361B2 (ja) | 2011-05-31 | 2011-05-31 | 半導体装置 |
US13/410,658 US8791568B2 (en) | 2011-05-31 | 2012-03-02 | Semiconductor device |
DE102012208246.8A DE102012208246B4 (de) | 2011-05-31 | 2012-05-16 | Halbleitervorrichtung |
CN201210172592.6A CN102810523B (zh) | 2011-05-31 | 2012-05-30 | 半导体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011122135A JP5855361B2 (ja) | 2011-05-31 | 2011-05-31 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014172866A Division JP2015008321A (ja) | 2014-08-27 | 2014-08-27 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012253058A JP2012253058A (ja) | 2012-12-20 |
JP5855361B2 true JP5855361B2 (ja) | 2016-02-09 |
Family
ID=47173540
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011122135A Active JP5855361B2 (ja) | 2011-05-31 | 2011-05-31 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8791568B2 (ja) |
JP (1) | JP5855361B2 (ja) |
CN (1) | CN102810523B (ja) |
DE (1) | DE102012208246B4 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160132499A (ko) | 2012-09-04 | 2016-11-18 | 미쓰비시덴키 가부시키가이샤 | 반도체장치 및 반도체장치의 제조방법 |
DE102014114973B4 (de) * | 2014-10-15 | 2020-10-01 | Infineon Technologies Ag | Einpress-Package mit Chipkontakt auf aktiver Fläche mit Beanspruchsschutz und Verfahren zur Herstellung desselben |
CN108369912B (zh) | 2015-12-14 | 2021-08-06 | 三菱电机株式会社 | 半导体装置及其制造方法 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL159822B (nl) * | 1969-01-02 | 1979-03-15 | Philips Nv | Halfgeleiderinrichting. |
US4394678A (en) * | 1979-09-19 | 1983-07-19 | Motorola, Inc. | Elevated edge-protected bonding pedestals for semiconductor devices |
JPS59188153A (ja) * | 1983-04-08 | 1984-10-25 | Hitachi Ltd | 多層配線を有する電子回路装置の製造方法 |
JPS6072253A (ja) * | 1983-09-28 | 1985-04-24 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JPS6228760Y2 (ja) * | 1986-02-27 | 1987-07-23 | ||
JPH0212950A (ja) * | 1988-06-30 | 1990-01-17 | Toshiba Corp | 半導体装置 |
JPH03153048A (ja) | 1989-11-10 | 1991-07-01 | Seiko Epson Corp | 半導体装置 |
JPH03284847A (ja) * | 1990-03-30 | 1991-12-16 | Matsushita Electron Corp | 半導体装置 |
JPH04286343A (ja) * | 1991-03-15 | 1992-10-12 | Sumitomo Electric Ind Ltd | 半導体装置のボンディング構造およびその製造方法 |
US5136364A (en) * | 1991-06-12 | 1992-08-04 | National Semiconductor Corporation | Semiconductor die sealing |
JPH0653270A (ja) * | 1991-09-13 | 1994-02-25 | Hitachi Ltd | 半導体装置 |
JP2916326B2 (ja) | 1992-06-11 | 1999-07-05 | 三菱電機株式会社 | 半導体装置のパッド構造 |
JP2000299342A (ja) * | 1999-04-15 | 2000-10-24 | Matsushita Electric Ind Co Ltd | バンプ電極及びその製造方法 |
JP3387083B2 (ja) * | 1999-08-27 | 2003-03-17 | 日本電気株式会社 | 半導体装置及びその製造方法 |
DE10106564B4 (de) | 2001-02-13 | 2006-04-20 | Promos Technologies, Inc. | Bondierungsanschlussflächenanordnung |
JP3661695B2 (ja) * | 2003-07-11 | 2005-06-15 | 株式会社デンソー | 半導体装置 |
JP2005072203A (ja) * | 2003-08-22 | 2005-03-17 | Seiko Epson Corp | 端子電極、半導体装置、半導体モジュール、電子機器および半導体装置の製造方法 |
US8368211B2 (en) * | 2004-03-11 | 2013-02-05 | International Rectifier Corporation | Solderable top metalization and passivation for source mounted package |
JP2006049427A (ja) | 2004-08-02 | 2006-02-16 | Nec Electronics Corp | 半導体装置の製造方法 |
JP2007258596A (ja) * | 2006-03-24 | 2007-10-04 | Fujifilm Corp | 半導体素子の製造方法及び半導体素子 |
JP4812673B2 (ja) * | 2007-03-28 | 2011-11-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5214936B2 (ja) | 2007-09-21 | 2013-06-19 | 富士電機株式会社 | 半導体装置 |
JP2009200067A (ja) * | 2008-02-19 | 2009-09-03 | Panasonic Corp | 半導体チップおよび半導体装置 |
JP5177551B2 (ja) * | 2008-12-26 | 2013-04-03 | 住友電工デバイス・イノベーション株式会社 | 半導体装置 |
JP5327233B2 (ja) * | 2009-07-08 | 2013-10-30 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
JP2011122135A (ja) | 2009-10-07 | 2011-06-23 | Adeka Corp | 脂肪酸メチルエステル用低温流動性向上剤 |
-
2011
- 2011-05-31 JP JP2011122135A patent/JP5855361B2/ja active Active
-
2012
- 2012-03-02 US US13/410,658 patent/US8791568B2/en active Active
- 2012-05-16 DE DE102012208246.8A patent/DE102012208246B4/de active Active
- 2012-05-30 CN CN201210172592.6A patent/CN102810523B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
DE102012208246A1 (de) | 2012-12-06 |
DE102012208246B4 (de) | 2017-04-06 |
CN102810523A (zh) | 2012-12-05 |
US8791568B2 (en) | 2014-07-29 |
CN102810523B (zh) | 2016-07-06 |
US20120306079A1 (en) | 2012-12-06 |
JP2012253058A (ja) | 2012-12-20 |
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