JP5754543B2 - 半導体装置 - Google Patents
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Description
実施の形態1にかかる半導体装置について、逆阻止IGBTを例に説明する。図1は、本発明の実施の形態1にかかる逆阻止IGBTの構成を示す断面図である。図1に示すように、この逆阻止IGBTは、n-ドリフト領域1aとなるFZシリコン基板(半導体基板)上に、活性領域200と、活性領域200の外側に設けられる耐圧構造領域100と、耐圧構造領域100の外側に設けられる分離部130とを備えている。半導体基板の厚さは、例えば600V耐圧クラスの逆阻止IGBTの特性に悪影響を及ぼさないためには、例えば90μm以上であればよく、n-ドリフト領域1aは80μm以上であればよい。活性領域200には、n-ドリフト領域1aの基板おもて面側に設けられたトレンチゲートMOS構造およびn-ドリフト領域1aの基板裏面側に設けられたpコレクタ領域10aおよびコレクタ電極11aを有する縦型の逆阻止IGBTが構成されている。トレンチゲートMOS構造の詳細な説明については後述する。
実施の形態2にかかる半導体装置について、逆阻止IGBTを例に説明する。図18は、本発明の実施の形態2にかかる逆阻止IGBTの構成を示す断面図である。図19は、図18の逆阻止IGBTの活性領域の構成を示す断面図である。図20は、図18の逆阻止IGBTの耐圧構造領域の構成を示す断面図である。実施の形態2にかかる逆阻止IGBTが実施の形態1にかかる逆阻止IGBTと異なる点は、nシェル領域に代えて、n-ドリフト領域1aの内部のpコレクタ領域10a近傍にn型高濃度領域45を設けた点である。
2、2a pベース領域
2b 基板裏面側のpベース領域
3、3a n+エミッタ領域
4、4a p+ボディ領域
5 第1トレンチ
5a 第2トレンチ
6、6a ゲート絶縁膜
7、7a ゲート電極
8、8a 絶縁膜、層間絶縁膜
8b フィールド絶縁膜
9、9a エミッタ電極
10、10a pコレクタ領域
11、11a コレクタ電極
12 nLCS領域
13 nシェル領域(第1シェル領域)
13a nシェル領域(第2シェル領域)
14 フィールドプレート
15 裏面側電極
20 pベース接合
21 コレクタ接合
21a 分離領域接合
31a 分離領域
100 耐圧構造領域
101 フィールドリミッティングリング
200 活性領域
Claims (7)
- 第1導電型の半導体基板からなるドリフト領域と、
前記半導体基板の一方の主面の表面層に選択的に設けられた第2導電型のベース領域と、
前記ベース領域の内部に選択的に設けられた第1導電型のエミッタ領域と、
前記半導体基板の一方の主面から前記エミッタ領域および前記ベース領域を貫通して前記ドリフト領域に達するトレンチと、
前記トレンチの内壁に沿って設けられた絶縁膜と、
前記トレンチの内部に前記絶縁膜を介して埋め込まれるゲート電極と、
前記エミッタ領域および前記ベース領域に接するエミッタ電極と、
前記ドリフト領域の内部に設けられ、前記ベース領域の前記ドリフト領域側に接する第1導電型のシェル領域と、
前記半導体基板の他方の主面の表面層に設けられた第2導電型のコレクタ領域と、
を備え、
前記シェル領域は、前記ドリフト領域よりも高い不純物濃度を有し、
前記シェル領域中の第1導電型の不純物の実効ドーズ量が5.0×1012cm-2以下であり、
前記トレンチは、前記シェル領域を貫通する深さを有し、
前記ドリフト領域は、前記エミッタ電極を正極とする逆方向の定格電圧印加時に前記コレクタ領域から拡がる空乏層が前記トレンチの底部に到達しない抵抗率を有することを特徴とする半導体装置。 - 前記シェル領域中の第1導電型の不純物の実効ドーズ量が4.0×1012cm-2以下であることを特徴とする請求項1に記載の半導体装置。
- 前記ドリフト領域と前記コレクタ領域との間に、漏れ電流を低減させるための、前記ドリフト領域よりも高い不純物濃度を有する第1導電型領域が設けられていることを特徴とする請求項1に記載の半導体装置。
- 前記ドリフト領域の外周端部に、前記半導体基板の一方の主面から前記コレクタ領域に達する第2導電型の分離領域をさらに備えることを特徴とする請求項1に記載の半導体装置。
- 前記ドリフト領域は、前記エミッタ電極を正極とする逆方向の定格電圧印加時、前記コレクタ領域から前記ベース領域に向かって拡がる空乏層が前記ベース領域もしくは前記トレンチの底部のうち前記コレクタ領域に近い方に到達しない抵抗率を有することを特徴とする請求項1に記載の半導体装置。
- 第1導電型の半導体基板からなるドリフト領域と、
前記半導体基板の一方の主面の表面層に選択的に設けられた第2導電型の第1ベース領域と、
前記第1ベース領域の内部に選択的に設けられた第1導電型の第1エミッタ領域と、
前記半導体基板の一方の主面から前記第1エミッタ領域および前記第1ベース領域を貫通して前記ドリフト領域に到達する第1トレンチと、
前記第1トレンチの内壁に沿って設けられた第1絶縁膜と、
前記第1トレンチの内部に前記第1絶縁膜を介して埋め込まれた第1ゲート電極と、
前記第1エミッタ領域および前記第1ベース領域に接するエミッタ電極と、
前記ドリフト領域の内部に設けられ、前記第1ベース領域の前記ドリフト領域側に接する第1導電型の第1シェル領域と、
前記半導体基板の他方の主面の表面層に選択的に設けられた第2導電型の第2ベース領域と、
前記第2ベース領域の内部に選択的に設けられた第1導電型の第2エミッタ領域と、
前記半導体基板の他方の主面から前記第2エミッタ領域および前記第2ベース領域を貫通して前記ドリフト領域に到達する第2トレンチと、
前記第2トレンチの内壁に沿って設けられた第2絶縁膜と、
前記第2トレンチの内部に前記第2絶縁膜を介して埋め込まれた第2ゲート電極と、
前記第2エミッタ領域および前記第2ベース領域に接する裏面電極と、
前記ドリフト領域の内部に設けられ、前記第2ベース領域の前記ドリフト領域側に接する第1導電型の第2シェル領域と、
を備え、
前記第1シェル領域および前記第2シェル領域は、前記ドリフト領域よりも高い不純物濃度を有し、
前記第1シェル領域および前記第2シェル領域中の第1導電型の不純物の実効ドーズ量が5.0×1012cm-2以下であり、
前記第1トレンチは、前記第1シェル領域を貫通する深さを有し、
前記ドリフト領域は、前記エミッタ電極を正極とする逆方向の定格電圧印加時に前記第2ベース領域から拡がる空乏層が前記第1トレンチの底部に到達しない抵抗率を有することを特徴とする半導体装置。 - 前記第2シェル領域中の第1導電型の不純物の実効ドーズ量が4.0×1012cm-2以下であることを特徴とする請求項6に記載の半導体装置。
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PCT/JP2013/053438 WO2013136898A1 (ja) | 2012-03-16 | 2013-02-13 | 半導体装置 |
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DE112014001689T5 (de) * | 2013-03-28 | 2015-12-10 | Abb Technology Ag | Verfahren zur Herstellung eines Bipolartransistors mit isolierter Gateelektrode |
US9742385B2 (en) | 2013-06-24 | 2017-08-22 | Ideal Power, Inc. | Bidirectional semiconductor switch with passive turnoff |
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US9355853B2 (en) | 2013-12-11 | 2016-05-31 | Ideal Power Inc. | Systems and methods for bidirectional device fabrication |
US11637016B2 (en) | 2013-12-11 | 2023-04-25 | Ideal Power Inc. | Systems and methods for bidirectional device fabrication |
JP6109098B2 (ja) * | 2014-02-18 | 2017-04-05 | 三菱電機株式会社 | 絶縁ゲート型半導体装置 |
JP6231422B2 (ja) * | 2014-04-09 | 2017-11-15 | トヨタ自動車株式会社 | 半導体装置 |
US9660551B2 (en) | 2014-11-06 | 2017-05-23 | Ideal Power, Inc. | Operating point optimization with double-base-contact bidirectional bipolar junction transistor circuits, methods, and systems |
JP6606819B2 (ja) * | 2014-11-10 | 2019-11-20 | 富士電機株式会社 | 半導体装置 |
JP6353804B2 (ja) * | 2015-03-27 | 2018-07-04 | 株式会社 日立パワーデバイス | 半導体装置及びそれを用いた電力変換装置 |
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JP2017045874A (ja) * | 2015-08-27 | 2017-03-02 | 株式会社東芝 | 半導体装置 |
JP6614326B2 (ja) * | 2016-02-15 | 2019-12-04 | 富士電機株式会社 | 半導体装置 |
JP6701789B2 (ja) * | 2016-02-19 | 2020-05-27 | 富士電機株式会社 | Rb‐igbt |
DE112017000079T5 (de) | 2016-03-10 | 2018-05-17 | Fuji Electric Co., Ltd. | Halbleitervorrichtung |
DE102016112721B4 (de) * | 2016-07-12 | 2022-02-03 | Infineon Technologies Ag | n-Kanal-Leistungshalbleitervorrichtung mit p-Schicht im Driftvolumen |
CN108321188B (zh) * | 2017-01-18 | 2021-02-09 | 中芯国际集成电路制造(上海)有限公司 | 绝缘栅双极型晶体管及其形成方法 |
JP6972691B2 (ja) * | 2017-06-19 | 2021-11-24 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP7143575B2 (ja) * | 2017-07-18 | 2022-09-29 | 富士電機株式会社 | 半導体装置 |
CN107731901B (zh) * | 2017-11-20 | 2024-02-23 | 电子科技大学 | 一种逆阻型igbt |
JP7068981B2 (ja) * | 2018-09-25 | 2022-05-17 | 三菱電機株式会社 | 半導体装置 |
US11069770B2 (en) * | 2018-10-01 | 2021-07-20 | Ipower Semiconductor | Carrier injection control fast recovery diode structures |
CN111261710A (zh) * | 2018-12-03 | 2020-06-09 | 珠海格力电器股份有限公司 | 一种绝缘栅双极型晶体管及其制备方法 |
CN110534582B (zh) * | 2019-09-28 | 2023-02-28 | 上海芯石微电子有限公司 | 一种具有复合结构的快恢复二极管及其制造方法 |
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JP3395520B2 (ja) | 1996-06-04 | 2003-04-14 | 富士電機株式会社 | 絶縁ゲートバイポーラトランジスタ |
JP2002532885A (ja) | 1998-12-04 | 2002-10-02 | インフィネオン テクノロジース アクチエンゲゼルシャフト | 出力半導体回路 |
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JP2008277352A (ja) | 2007-04-25 | 2008-11-13 | Matsushita Electric Ind Co Ltd | 半導体装置 |
DE102009005914B4 (de) * | 2008-01-28 | 2014-02-13 | Denso Corporation | Halbleitervorrichtung mit Halbleiterelement mit isoliertem Gate und bipolarer Transistor mit isoliertem Gate |
JP2010219361A (ja) * | 2009-03-18 | 2010-09-30 | Toshiba Corp | 半導体装置及びその製造方法 |
DE102010063728B4 (de) | 2009-12-28 | 2016-04-14 | Fuji Electric Co., Ltd. | Halbleitervorrichtung mit verbesserter Sperrspannungsfestigkeit |
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