JP5686824B2 - 高速回復整流器構造体の装置および方法 - Google Patents
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Description
本出願は2005年12月27日に出願されるとともに本発明の譲受人に譲受された"Fast Recovery Rectifier Structure"と題された同時係属仮特許出願第60/754,550号の優先権を主張するものであり、その全体を本明細書に引用して援用する。
発明の背景
発明の分野
本発明の実施形態は整流器の分野に関する。特に本発明の実施形態は概して高速回復整流器構造体に関する。
スイッチング電源の効率における重要な要因はそのような回路で用いられるダイオードの性能である。特にそのようなダイオードの逆回復は、そのような電源のトランジスタスイッチのターンオン・ロスを低減することができる。例えば逆回復電流過渡がスイッチのターンオン時に電流の付加成分として出現し、スイッチのターンオン・ロスはそのような逆回復成分がない場合より大幅に高いという結果になる。その結果逆回復電荷(Qrr)を低減することがスイッチング電源の効率の改善に重要である。
そのためソフトリカバリ特性を維持する逆回復電荷が低減した高速回復整流器構造体が非常に望まれている。さらなる要求はより小型形状用のトレンチを用いて形成された高速回復整流器構造体で、上記の要求を満たすことである。さらに他の要求はこれが従来の半導体製造プロセスおよび機器と適合し且つ相補的であるように、上記の要求を満たすことである。
ここで本発明の好適な実施形態、高速回復整流器構造体および構造体の作製方法を詳細に参照して、それらの例を添付の図面で説明する。好適な実施形態に関連して本発明を説明するが、本発明をこれらの実施形態に限定しようとするものではないことは理解されよう。反対に本発明は添付の特許請求の範囲に規定された本発明の要旨と範囲とにある変更例、同等物および代替例をすべて網羅しようとするものである。
Claims (16)
- 第1のドーパント型がドープされた第2のエピタキシャル層を、前記第2のエピタキシャル層より高濃度に前記第1のドーパント型がドープされた基板上に堆積するステップと、
前記第1のドーパント型が低濃度にドープされた第1のエピタキシャル層を、前記第1のエピタキシャル層より高濃度にドープされた前記第2のエピタキシャル層上に堆積するステップと、
複数のトレンチを前記第1のエピタキシャル層内にエッチングするステップであって、前記複数のトレンチそれぞれの幅を0.5μmよりも小さくし、かつ、トレンチとトレンチの間隔を0.65μmよりも小さくするステップと、
前記複数のトレンチの各々の壁および底部上に複数の酸化物層を形成するステップと、 各々互いに離間されるとともに、各々対応するトレンチから電気的に絶縁された複数のウェルに、前記複数のトレンチの各々の底部付近で第2のドーパント型を注入するステップと、
前記第1のドーパント型を、前記複数のウェル間に規定される複数のチャネル領域内の前記第1のエピタキシャル層に注入するステップと、ここで、前記複数のチャネル領域は前記第1のエピタキシャル層より高濃度にドープされており、
第1の金属層を前記第1のエピタキシャル層上に堆積するステップと
を含む整流器構造体の作製方法。 - ショットキー障壁が前記第1の金属層と前記第1のエピタキシャル層とを離間するように、前記第1の金属層の下にショットキー障壁を堆積するステップさらに含む、請求項1に記載の方法。
- 前記複数のトレンチのうちの2つの間隔及び当該2つのトレンチの深さを、ショットキー障壁対PiN比が1以上になるよう選択した、請求項2に記載の方法。
- 前記複数のトレンチのうちの2つの間隔は0.45μm〜0.65μmの間であり、第1及び第2のトレンチの深さは300nm〜700nmの間である、請求項3に記載の方法。
- 前記複数のトレンチのうちの2つの幅は0.4μm〜0.5μmの間である、請求項4に記載の方法。
- 前記複数のウェルのそれぞれは、150nm〜200nmの間の幅で、200nm〜300nmの間の深さである、請求項1又は5に記載の方法。
- さらに、前記複数のウェルおよび前記第1の金属層に結合された複数の互いに遠隔に位置するコンタクト領域を形成するステップを含む、請求項1又は3に記載の方法。
- 前記複数のトレンチのそれぞれは、非ドープシリコンを含んでいる、請求項1に記載の方法。
- 超高速ダイオードの作製方法であって、
第1のドーパント型が低濃度にドープされた第1のエピタキシャル層を、前記第1のエピタキシャル層より高濃度に前記第1のドーパント型がドープされた基板上に堆積するステップと、
前記第1のエピタキシャル層内に第1及び第2のトレンチをエッチングするステップであって、前記第1及び第2のトレンチそれぞれの幅を0.5μmよりも小さくし、かつ、前記第1及び第2のトレンチの間隔を0.65μmよりも小さくするステップと、
前記第1のトレンチの底部付近で第1のウェルに第2のドーパント型を注入するとともに、前記第2のトレンチの底部付近で第2のウェルに第2のドーパント型を注入するステップと、ここで、前記複数のウェルは互いに離間されており、
前記第1のエピタキシャル層内であって前記第1のウェルと前記第2のウェルの間に位置するチャネル領域を形成するステップと、ここで、前記チャネル領域は、前記第1のドーパント型で前記第1のエピタキシャル層よりも高濃度にドープされており、
第1の金属層を前記第1のエピタキシャル層上に堆積するステップと、
を含む方法。 - さらに、第1のエピタキシャル層を堆積する前に、前記基板上に、基板より低濃度で、かつ、第1のエピタキシャル層よりも高濃度に第1のドーパント型でドープされた第2のエピタキシャル層を堆積するステップを含む、請求項9に記載の方法。
- 第1の金属層を堆積する前に、ショットキー障壁が前記第1の金属層の下に配置され、かつ、前記第1の金属層と前記第1のエピタキシャル層とを分離するように、前記ショットキー障壁を堆積するステップを含む、請求項9に記載の方法。
- ショットキー障壁対PiN比が1以上になるように、前記第1及び第2のトレンチの間隔並びに前記第1及び第2のトレンチの深さを選択する、請求項11に記載の方法。
- さらに、前記第1及び第2トレンチの各々の壁及び底部上に酸化物層を、第1及び第2のウェルが対応するトレンチから電気的に絶縁されるように形成するステップを含む、請求項9に記載の方法。
- 前記第1及び第2のトレンチの間隔は0.45μm〜0.65μmの間であり、前記第1及び第2のトレンチの深さは300nm〜700nmの間である、請求項12に記載の方法。
- 前記第1及び第2のトレンチの幅は、0.4μm〜0.5μmの間である、請求項14に記載の方法。
- 前記第1及び第2のウェルは、150nm〜200nmの間の幅であり、200nm〜300nmの間の深さである、請求項9又は15に記載の方法。
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