JP5389752B2 - 電子部品パッケージの製造方法 - Google Patents
電子部品パッケージの製造方法 Download PDFInfo
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Description
以下、本発明の実施の形態について図面を参照して詳細に説明する。始めに、図1ないし図4を参照して、本発明の第1の実施の形態に係る電子部品パッケージの製造方法、電子部品パッケージ用ウェハおよび電子部品パッケージ用基礎構造物の概略について説明する。
次に、図31ないし図33を参照して、本発明の第2の実施の形態について説明する。本実施の形態に係る電子部品パッケージの製造方法は、図15および図16に示したように封止部材25を形成する工程までは第1の実施の形態と同様である。
次に、本発明の第3の実施の形態について説明する。まず、本実施の形態におけるウェハ1を作製する工程について、図34ないし図38を参照して説明する。本実施の形態に係る電子部品パッケージの製造方法では、まず、リードフレーム60を作製する。図34は、リードフレーム60の一部を示す平面図である。このリードフレーム60は、複数の電子部品パッケージに対応した複数組の外部接続端子11と、この複数組の外部接続端子11を連結する連結部13とを含んでいる。リードフレーム60は、チップ接合用導体層12を含んでいない。リードフレーム60の作製方法は、第1の実施の形態におけるリードフレーム10と同様である。
次に、本発明の第4の実施の形態について説明する。まず、本実施の形態におけるウェハ1を作製する工程について、図41ないし図47を参照して説明する。ウェハ1を作製する工程では、まず、リードフレーム10を作製する。図41は、リードフレーム10の一部を示す平面図である。このリードフレーム10は、複数の電子部品パッケージに対応した複数組の外部接続端子11と、複数の電子部品パッケージに対応した複数のチップ接合用導体層12と、これら外部接続端子11およびチップ接合用導体層12を連結する連結部13とを含んでいる。なお、本実施の形態におけるリードフレーム10では、各外部接続端子11の一端は連結部13に接続され、各外部接続端子11の他端はチップ接合用導体層12に接続されている。リードフレーム10の作製方法は、第1の実施の形態と同様である。
Claims (7)
- 複数の外部接続端子を有する基体と、前記基体に接合され且つ前記複数の外部接続端子の少なくとも1つに電気的に接続された少なくとも1つの電子部品チップとを備えた電子部品パッケージを製造する方法であって、
複数の電子部品パッケージに対応した複数組の外部接続端子と、前記複数組の外部接続端子を保持する保持部とを有し、それぞれ後に互いに分離されることによって前記基体となる複数の基体予定部を含むウェハを作製する工程と、
前記ウェハにおける各基体予定部にそれぞれ少なくとも1つの電子部品チップを接合する工程と、
前記基体予定部に電子部品チップを接合する工程の後で、各基体予定部を互いに分離して、複数の基体を形成する工程とを備え、
前記ウェハは、上面と下面を有し、
前記基体は、前記ウェハの上面および下面に対応する上面および下面と、この上面と下面を連結する側面とを有し、
前記保持部は、前記基体予定部に配置された基体構成部と、前記基体構成部を構成する材料とは異なる材料によって構成され、前記基体予定部の周囲に配置された除去予定部とを有し、前記各外部接続端子は、前記基体構成部と除去予定部とにまたがって配置され、
前記複数の基体を形成する工程は、各基体予定部が互いに分離されるように、前記除去予定部の位置で前記ウェハを切断する工程と、前記ウェハを切断する工程の後で、前記除去予定部を除去することによって、前記複数の外部接続端子の各々における一部が前記基体の側面から突出するように、前記基体の側面を形成する工程とを含むことを特徴とする電子部品パッケージの製造方法。 - 前記ウェハは、更に、前記複数の基体予定部にそれぞれ配置され、各々に前記少なくとも1つの電子部品チップが接合される複数のチップ接合用導体層を有することを特徴とする請求項1記載の電子部品パッケージの製造方法。
- 前記電子部品チップは複数の電極を有し、前記電子部品パッケージは、それぞれ少なくとも1つの前記電極と少なくとも1つの前記外部接続端子とを接続する複数の端子用接続部を備え、
電子部品パッケージの製造方法は、更に、前記基体予定部に電子部品チップを接合する工程と前記ウェハを切断する工程との間において前記端子用接続部を形成する工程を備えたことを特徴とする請求項1または2記載の電子部品パッケージの製造方法。 - 前記各基体予定部は上面を有し、前記上面は、前記少なくとも1つの電子部品チップが接合されるチップ接合面と、前記端子用接続部が接続される前記外部接続端子における接続面とを含み、前記接続面は前記チップ接合面よりも上方に配置されていることを特徴とする請求項3記載の電子部品パッケージの製造方法。
- 前記端子用接続部を形成する工程は、前記ウェハおよび電子部品チップを覆い、平坦化された上面を有する絶縁層を形成する工程と、前記絶縁層に、前記外部接続端子および電極を露出させるための複数の開口部を形成する工程と、その一部が前記開口部に挿入されるように、めっき法によって前記端子用接続部を形成する工程とを含むことを特徴とする請求項3または4記載の電子部品パッケージの製造方法。
- 前記電子部品パッケージは、複数の前記電子部品チップを備え、更に、前記複数の電子部品チップの電極同士を電気的に接続する少なくとも1つのチップ間接続部を備え、
前記チップ間接続部は、前記端子用接続部が形成される際に同時に形成されることを特徴とする請求項3ないし5のいずれかに記載の電子部品パッケージの製造方法。 - 更に、前記基体予定部に電子部品チップを接合する工程と前記ウェハを切断する工程との間において、前記電子部品チップを封止する封止部材を形成する工程を備えたことを特徴とする請求項1ないし6のいずれかに記載の電子部品パッケージの製造方法。
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US9016552B2 (en) * | 2013-03-15 | 2015-04-28 | Sanmina Corporation | Method for forming interposers and stacked memory devices |
US20160064299A1 (en) * | 2014-08-29 | 2016-03-03 | Nishant Lakhera | Structure and method to minimize warpage of packaged semiconductor devices |
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