JP5199072B2 - チャネル領域の平滑な表面を有するシリコンカーバイドデバイスを作製する方法 - Google Patents
チャネル領域の平滑な表面を有するシリコンカーバイドデバイスを作製する方法 Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
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- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
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Description
Claims (15)
- シリコンカーバイドパワーデバイスを形成する方法であって、
シリコンカーバイド基板上にn−シリコンカーバイド層を形成するステップ、
前記n−シリコンカーバイド層上にp型シリコンカーバイドウェル領域を形成するために、前記n−シリコンカーバイド層内にp型ドーパントを注入するステップ、または、前記n−シリコンカーバイド層上にp型エピタキシャル層を形成するステップ、
前記p型シリコンカーバイドウェル領域内にp+シリコンカーバイドの埋込み領域を形成するために、前記p型シリコンカーバイドウェル領域内にp型ドーパントを注入するステップ、
n型ドーパントをp+シリコンカーバイドの埋込み領域上のp型シリコンカーバイドウェルにインプラントして、p+シリコンカーバイドの埋込み領域上に、シリコンカーバイドのn+領域を形成するステップであって、パワーデバイスのチャネル領域はp+の埋込み領域とシリコンカーバイドのn+領域に隣接し、
前記チャネル領域上に、再成長プロセスでn−シリコンカーバイドエピタキシャル領域を形成するステップ、および、
前記チャネル領域から前記n−領域の表面の一部分を化学機械研磨(CMP)プロセスで除去するステップであって、それにより、前記n−領域の一部分が、前記チャネル領域上に残って、前記チャネル領域の表面粗さを低減する、ことを特徴とする方法。 - 前記CMPプロセスは、前記チャネル領域から前記n−領域の、1000から5000Åを除く全てを除去することを特徴とする請求項1に記載の方法。
- 前記除去するステップは、前記チャネル領域の表面粗さの深さの2.0から3.0倍である前記n−領域の一部分を除去するステップをさらに含むことを特徴とする請求項1に記載の方法。
- 前記n−領域の1500Åは、前記CMPプロセス後に前記チャネル領域上に残ることを特徴とする請求項3に記載の方法。
- 前記表面粗さの低減は、28Åから1.0Åまでの2乗平均平方根(RMS)表面粗さの低減であることを特徴とする請求項1に記載の方法。
- 前記除去するステップは
前記チャネル領域上の前記n−領域の残りの部分上に、100から1000Åの厚さを有する犠牲酸化物層を形成するステップ、および、
前記犠牲酸化物層を除去するステップを続いて伴い、前記RMS表円面粗さは、前記犠牲酸化物層の形成および1.0Åから0.70Åまでの前記犠牲酸化物層の除去によってさらに低減されることを特徴とする請求項5に記載の方法。 - 前記n−領域を形成するステップは、前記チャネル領域上でn−エピタキシャル層を所定の厚さに成長させることであって、それにより、前記n−エピタキシャル層の一部分が、前記n−エピタキシャル層のその部分の除去後に、前記チャネル領域上に残るようにn−領域を成長させるステップを含むことを特徴とする請求項1に記載の方法。
- 前記n−エピタキシャル層の前記所定の厚さは、1500Åから6000Åであることを特徴とする請求項7に記載の方法。
- 前記CMPプロセスを実施するステップは、前記n−領域が、前記n+領域から除去されるように、前記n−領域を選択的にエッチングするステップを続いて伴うことを特徴とする請求項1に記載の方法。
- 前記注入されたドーパントを1600℃より高い温度にさらすことによって前記注入されたドーパントを活性化するステップをさらに含むことを特徴とする請求項1に記載の方法。
- 前記チャネル領域に隣接する前記p型シリコンカーバイドウェル領域内にシリコンカーバイドのn型領域を形成するステップをさらに含み、前記チャネル領域が、前記p+シリコンカーバイドの埋込み領域と前記シリコンカーバイドのn型領域との間に画定され、前記シリコンカーバイドのn型領域が、前記シリコンカーバイドパワーデバイスの接合型電界効果トランジスタ(Junction Field Effect Transistor)(JFET)領域であることを特徴とする請求項1に記載の方法。
- 前記チャネル領域に隣接する前記p型シリコンカーバイドウェル領域内にシリコンカーバイドのn型領域を形成するステップをさらに含み、前記チャネル領域が、前記p+シリコンカーバイドの埋込み領域と前記シリコンカーバイドのn型領域との間に画定され、前記n−領域が、前記チャネル領域上に残るだけであることを特徴とする請求項1に記載の方法。
- 前記基板は、前記シリコンカーバイドパワーデバイスのドリフト領域の役をするn−基板を含み、前記n−シリコンカーバイド層に対向するn+ドレイン領域を基板上に形成するステップをさらに含むことを特徴とする請求項1に記載の方法。
- 前記n+ドレイン領域を形成するステップは、前記n−基板内に前記n+ドレイン領域を注入するステップ、および、前記n−基板上で前記n+ドレイン領域を成長させるステップの少なくとも一方を含むことを特徴とする請求項13に記載の方法。
- 前記シリコンカーバイドパワーデバイスは、金属酸化物半導体電界効果トランジスタ(Metal Oxide Semiconductor Field Effect Transistor)(MOSFET)を含むことを特徴とする請求項1に記載の方法。
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US11/136,057 | 2005-05-24 | ||
US11/136,057 US7528040B2 (en) | 2005-05-24 | 2005-05-24 | Methods of fabricating silicon carbide devices having smooth channels |
PCT/US2006/009493 WO2006127093A2 (en) | 2005-05-24 | 2006-03-16 | Methods of fabricating silicon carbide devices having a smooth surface of the channel regions |
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EP (2) | EP1883951B1 (ja) |
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US20150028354A1 (en) | 2015-01-29 |
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