JP5178859B2 - 電子装置、表示装置 - Google Patents
電子装置、表示装置 Download PDFInfo
- Publication number
- JP5178859B2 JP5178859B2 JP2011038124A JP2011038124A JP5178859B2 JP 5178859 B2 JP5178859 B2 JP 5178859B2 JP 2011038124 A JP2011038124 A JP 2011038124A JP 2011038124 A JP2011038124 A JP 2011038124A JP 5178859 B2 JP5178859 B2 JP 5178859B2
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- transistor
- electrically connected
- gate
- wiring
- source
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Description
よって、デジタル階調方式と時間階調方式を組み合わせた場合、サステイン(点灯)期間は2のべき乗の比をもって長さが決まることから、1フレーム期間の長さを考えると、多階調化が困難になる。
前述のタイミングチャートにおいて、アドレス(書き込み)期間とサステイン(点灯)期間とが分離していない場合には、サステイン(点灯)期間の最小単位が制限されてしまうという問題点を述べた。この問題を解決するために、以下のような表示方法が提案された。
サステイン(点灯)期間では、EL駆動用TFT1702に印加されるゲート・ソース間電圧は、保持容量1704が保持している電荷によってまかなわれる。
すなわち、EL駆動用TFT1702に印加されるゲート・ソース間電圧は、保持容量1704の両端子間の電位差に等しい。サステイン(点灯)期間が終了し、非表示期間を設けるには、リセット信号線1712にリセット信号を入力して、リセット用TFT1705を導通状態にする。この動作により、リセット用TFT1705のソース領域とドレイン領域との間の電位差、すなわち保持容量1704の両端子間の電位差が0[V]となる。よってEL駆動用TFT1702のゲート・ソース間電圧が0[V]となって非導通状態となり、EL素子1703への電流供給が遮断される。直ちにリセット用TFT1705は非導通状態に戻るが、保持容量1704の両端子間の電位差は0[V]のまま保持されるので、EL駆動用TFT1702のゲート・ソース間電圧も引き続き0[V]であり、その後新たに画像信号が書き込まれるまでは、EL素子1703は点灯しない。この非表示期間は、アドレス(書き込み)期間の長さをta、サステイン(点灯)期間の長さをts、1ゲート信号線選択期間の長さをtg(ta、ts、tg>0)
として、非表示期間の長さをtr(tr>0)とすると、tr=ta−(ts+tg)で求められる長さを少なくとも有する。こうして、短いサステイン(点灯)期間を挟んだアドレス(書き込み)期間の重複を回避することが出来る。
期間Tanと、j+1フレーム目のサブフレーム期間SF1でのアドレス(書き込み)期間Ta1とが重複する場合に、jフレーム目のサブフレーム期間SFnでのサステイン(点灯)期間SFnの終了後、前記j+1フレーム目のサブフレーム期間SF1でのアドレス(書き込み)期間Ta1の開始までの期間に非表示期間を有することを特徴としている。
期間の長さをtak、サステイン(点灯)期間の長さをtsk、1ゲート信号線選択期間の長さをtg(tak、tsk、tg>0)として、tak>tsk+tgが成立するとき、 SFkの有する非表示期間の長さをtrk(trk>0)とすると、 常に、trk≧tak−(tsk+tg)が成立することを特徴としている。
したがって、ゲート信号線1706が選択されるときは電位が上がり、スイッチング用TFT1701が導通状態となる。
また、アドレス(書き込み)期間は、1行目のゲート信号線が選択されてから、最終行のゲート信号線の選択が終了するまでの期間であるので,Ta1〜Ta3は全て等長である。
この動作が1行目から最終行まで行われる。続いて、サブフレーム期間SF2においても同様に、ゲート信号線306が選択され、ソース信号線307から、画素への信号の書き込みが行われる。各行では、画素への信号の書き込みが終了すると、直ちにサステイン(点灯)期間SF2に移る。この動作が1行目から最終行まで行われる。
を任意に制御することができる。
例えば、プラズマCVD法でSiH4、NH3、N2Oから作製される酸化窒化シリコン膜5002aを10〜200[nm](好ましくは50〜100[nm])形成し、同様にSiH4、N2Oから作製される酸化窒化水素化シリコン膜5002bを50〜200[nm](好ましくは100〜150[nm])の厚さに積層形成する。本実施例では下地膜5002を2層構造として示したが、前記絶縁膜の単層膜または2層以上積層させた構造として形成しても良い。
ゲート絶縁膜上に残渣を残すことなくエッチングするためには、10〜20[%]程度の割合でエッチング時間を増加させると良い。W膜に対する酸化窒化シリコン膜の選択比は2〜4(代表的には3)であるので、オーバーエッチング処理により、酸化窒化シリコン膜が露出した面は20〜50[nm]程度エッチングされることになる。こうして、第1のエッチング処理により第1の導電層と第2の導電層から成る第1の形状の導電層5011〜5016(第1の導電層5011a〜5016aと第2の導電層5011b〜5016b)を形成する。このとき、ゲート絶縁膜5007においては、第1の形状の導電層5011〜5016で覆われない領域は20〜50[nm]程度エッチングされ薄くなった領域が形成される(図6(A))。
また、5031は島状のソース信号線として機能する。
厚のアルミニウム膜を形成する。勿論、公知の陰極材料であるMgAg電極を用いても良い。そして陰極4019は4020で示される領域において配線4007に接続される。配線4007は陰極4019に所定の電圧を与えるための電源線であり、導電性ペースト材料4021を介してFPC4008に接続される。
、エポキシ樹脂、シリコン樹脂、PVB(ポリビニルブチラル)またはEVA(エチレンビニルアセテート)を用いることができる。この充填材4023の内部に乾燥剤を設けておくと、吸湿効果を保持できるので好ましい。また充填材4023の内部に、酸素を捕捉する効果を有する酸化防止剤等を配置することで、EL層の劣化を抑えても良い。
画素部において、点線枠1800で囲まれた部分が、1画素分の回路である。拡大図を図18(B)に示す。
EL素子1803は、実施例4の図10に示した構造によって形成されるため、1810が陰極,1811が陽極、1809は陽極配線となる。
実施例7に示したように、EL駆動用TFTにNチャネル型を用いた構造をとっても良いが、本実施例においては、例として、実施例1にて示したように、EL駆動用TFTにPチャネル型を用いるものとして述べる。
(T.Tsutsui, C.Adachi, S.Saito, Photochemical Processes in Organized Molecular Systems, ed.K.Honda,(Elsevier Sci.Pub., Tokyo,1991)p.437.)
上記の論文により報告されたEL材料(クマリン色素)の分子式を以下に示す。
上記の論文により報告されたEL材料(Pt錯体)の分子式を以下に示す。
(T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T.Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38(12B)(1999)L1502.)
上記の論文により報告されたEL材料(Ir錯体)の分子式を以下に示す。
であり、本体3331、記録媒体(DVD等)3332、操作スイッチ3333、表示部(a)3334、表示部(b)3335等を含む。表示部(a)3334は主として画像情報を表示し、表示部(b)3335は主として文字情報を表示するが、本発明の電子装置およびその駆動方法はこれら表示部(a)3334、表示部(b)3335にて用いることが出来る。なお、記録媒体を備えた画像再生装置には家庭用ゲーム機器なども含まれる。
Claims (15)
- 第1のトランジスタのソースまたはドレインの一方に電気的に接続された第1の配線と、
第1のトランジスタのゲートに電気的に接続された第2の配線と、
保持容量の第1の電極と、第2のトランジスタのソース又はドレインの一方と、に電気的に接続された第3の配線と、
第3のトランジスタのゲートに電気的に接続された第4の配線と、
前記第2のトランジスタのソース又はドレインの他方に電気的に接続された画素電極と、を有する画素を複数有し、
前記第1のトランジスタのソース又はドレインの他方と、前記第2のトランジスタのゲートと、前記第3のトランジスタのソース又はドレインの一方と、前記保持容量の第2の電極と、は電気的に接続され、
一の前記画素における前記第3のトランジスタのソース又はドレインの他方は、他の一の前記画素における前記第2の配線と電気的に接続され、
前記第1の配線は、映像信号を伝えることができる機能を有し、
前記第2の配線は、前記第1のトランジスタをオン状態またはオフ状態にすることができる信号を伝えることができる機能を有し、
前記第3の配線は、前記画素電極に電流を伝えることができる機能を有し、
前記第4の配線は、前記第3のトランジスタをオン状態またはオフ状態にすることができる信号を伝えることができる機能を有することを特徴とする電子装置。 - 第1の配線と、第2の配線と、第3の配線と、第4の配線と、第5の配線と、第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、第1の電極及び第2の電極とを備えた保持容量と、画素電極と、を有する電子装置であって、
前記第1のトランジスタのソースまたはドレインの一方は、前記第1の配線と電気的に接続され、
前記第1のトランジスタのソースまたはドレインの他方は、前記第2のトランジスタのゲートと電気的に接続され、
前記第1のトランジスタのゲートは、前記第2の配線と電気的に接続され、
前記第2のトランジスタのソースまたはドレインの一方は、前記第3の配線と電気的に接続され、
前記第2のトランジスタのソースまたはドレインの他方は、前記画素電極と電気的に接続され、
前記保持容量の第1の電極は、前記第2のトランジスタのゲートと電気的に接続され、 前記保持容量の第2の電極は、前記第3の配線と電気的に接続され、
前記第3のトランジスタのソースまたはドレインの一方は、前記第2のトランジスタのゲートと電気的に接続され、
前記第3のトランジスタのソースまたはドレインの他方は、前記第5の配線と電気的に接続され、
前記第3のトランジスタのゲートは、前記第4の配線と電気的に接続され、
前記第1の配線は、映像信号を伝えることができる機能を有し、
前記第2の配線は、前記第1のトランジスタをオン状態またはオフ状態にすることができる信号を伝えることができる機能を有し、
前記第3の配線は、前記画素電極に電流を伝えることができる機能を有し、
前記第4の配線は、前記第3のトランジスタをオン状態またはオフ状態にすることができる信号を伝えることができる機能を有し、
前記第5の配線は、前記第1乃至第3のトランジスタ以外の第4のトランジスタをオン状態またはオフ状態にすることができる信号を伝えることができる機能を有し、
前記第4のトランジスタは、別の行の画素に信号を書き込む時のスイッチング素子としての機能を有することを特徴とする電子装置。 - ソース信号線と、第1のゲート信号線と、電流供給線と、リセット信号線と、第2のゲート信号線と、第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、第1の電極及び第2の電極とを備えた保持容量と、画素電極と、を有する電子装置であって、
前記第2のゲート信号線は、別の行の画素に信号を書き込む時のスイッチング素子をオン状態又はオフ状態にすることができる信号を伝えることができる機能を有し、
前記第1のトランジスタのソースまたはドレインの一方は、前記ソース信号線と電気的に接続され、
前記第1のトランジスタのソースまたはドレインの他方は、前記第2のトランジスタのゲートと電気的に接続され、
前記第1のトランジスタのゲートは、前記第1のゲート信号線と電気的に接続され、
前記第2のトランジスタのソースまたはドレインの一方は、前記電流供給線と電気的に接続され、
前記第2のトランジスタのソースまたはドレインの他方は、前記画素電極と電気的に接続され、
前記保持容量の第1の電極は、前記第2のトランジスタのゲートと電気的に接続され、 前記保持容量の第2の電極は、前記電流供給線と電気的に接続され、
前記第3のトランジスタのソースまたはドレインの一方は、前記第2のトランジスタのゲートと電気的に接続され、
前記第3のトランジスタのソースまたはドレインの他方は、前記第2のゲート信号線と電気的に接続され、
前記第3のトランジスタのゲートは、前記リセット信号線と電気的に接続されていることを特徴とする電子装置。 - 第1のトランジスタのソースまたはドレインの一方に電気的に接続されたソース信号線と、
第1のトランジスタのゲートに電気的に接続されたゲート信号線と、
保持容量の第1の電極と、第2のトランジスタのソース又はドレインの一方と、に電気的に接続された電流供給線と、
第3のトランジスタのゲートに電気的に接続されたリセット信号線と、
前記第2のトランジスタのソース又はドレインの他方に電気的に接続されたEL素子と、を有する画素を複数有し、
前記第1のトランジスタのソース又はドレインの他方と、前記第2のトランジスタのゲートと、前記第3のトランジスタのソース又はドレインの一方と、前記保持容量の第2の電極と、は電気的に接続され、
一の前記画素における前記第3のトランジスタのソース又はドレインの他方は、他の一の前記画素における前記ゲート信号線と電気的に接続されていることを特徴とする表示装置。 - 第1の配線と、第2の配線と、第3の配線と、第4の配線と、第5の配線と、第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、第1の電極及び第2の電極とを備えた保持容量と、EL素子と、を有する表示装置であって、
前記第1のトランジスタのソースまたはドレインの一方は、前記第1の配線と電気的に接続され、
前記第1のトランジスタのソースまたはドレインの他方は、前記第2のトランジスタのゲートと電気的に接続され、
前記第1のトランジスタのゲートは、前記第2の配線と電気的に接続され、
前記第2のトランジスタのソースまたはドレインの一方は、前記第3の配線と電気的に接続され、
前記第2のトランジスタのソースまたはドレインの他方は、前記EL素子と電気的に接続され、
前記保持容量の第1の電極は、前記第2のトランジスタのゲートと電気的に接続され、 前記保持容量の第2の電極は、前記第3の配線と電気的に接続され、
前記第3のトランジスタのソースまたはドレインの一方は、前記第2のトランジスタのゲートと電気的に接続され、
前記第3のトランジスタのソースまたはドレインの他方は、前記第5の配線と電気的に接続され、
前記第3のトランジスタのゲートは、前記第4の配線と電気的に接続され、
前記第1の配線は、映像信号を伝えることができる機能を有し、
前記第2の配線は、前記第1のトランジスタをオン状態またはオフ状態にすることができる信号を伝えることができる機能を有し、
前記第3の配線は、前記EL素子に電流を伝えることができる機能を有し、
前記第4の配線は、前記第3のトランジスタをオン状態またはオフ状態にすることができる信号を伝えることができる機能を有し、
前記第5の配線は、前記第1乃至第3のトランジスタ以外の第4のトランジスタをオン状態またはオフ状態にすることができる信号を伝えることができる機能を有し、
前記第4のトランジスタは、別の行の画素に信号を書き込む時のスイッチング素子としての機能を有することを特徴とする表示装置。 - ソース信号線と、第1のゲート信号線と、電流供給線と、リセット信号線と、第2のゲート信号線と、第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、第1の電極及び第2の電極とを備えた保持容量と、EL素子と、を有する表示装置であって、
前記第2のゲート信号線は、別の行の画素に信号を書き込む時のスイッチング素子をオン状態又はオフ状態にすることができる信号を伝えることができる機能を有し、
前記第1のトランジスタのソースまたはドレインの一方は、前記ソース信号線と電気的に接続され、
前記第1のトランジスタのソースまたはドレインの他方は、前記第2のトランジスタのゲートと電気的に接続され、
前記第1のトランジスタのゲートは、前記第1のゲート信号線と電気的に接続され、
前記第2のトランジスタのソースまたはドレインの一方は、前記電流供給線と電気的に接続され、
前記第2のトランジスタのソースまたはドレインの他方は、前記EL素子と電気的に接続され、
前記保持容量の第1の電極は、前記第2のトランジスタのゲートと電気的に接続され、 前記保持容量の第2の電極は、前記電流供給線と電気的に接続され、
前記第3のトランジスタのソースまたはドレインの一方は、前記第2のトランジスタのゲートと電気的に接続され、
前記第3のトランジスタのソースまたはドレインの他方は、前記第2のゲート信号線と電気的に接続され、
前記第3のトランジスタのゲートは、前記リセット信号線と電気的に接続されていることを特徴とする表示装置。 - 請求項1乃至請求項3のいずれか一項において、
前記第2のトランジスタはマルチゲート構造を有することを特徴とする電子装置。 - 請求項1又は請求項3において、
前記第2のトランジスタと並列接続された第4のトランジスタをそれぞれの前記画素に有することを特徴とする電子装置。 - 請求項4乃至請求項6のいずれか一項において、
前記第2のトランジスタはマルチゲート構造を有することを特徴とする表示装置。 - 請求項4又は請求項6において、
前記第2のトランジスタと並列接続された第4のトランジスタをそれぞれの前記画素に有することを特徴とする表示装置。 - 請求項4乃至請求項6のいずれか一項において、
前記EL素子は燐光材料を有することを特徴とする表示装置。 - 第1のトランジスタのソースまたはドレインの一方に電気的に接続された第1の配線と、
第1のトランジスタのゲートに電気的に接続された第2の配線と、
保持容量の第1の電極と、第2のトランジスタのソース又はドレインの一方と、に電気的に接続された第3の配線と、
第3のトランジスタのゲートに電気的に接続された第4の配線と、
前記第2のトランジスタのソース又はドレインの他方に電気的に接続されたEL素子と、を有する画素を複数有し、
前記第1のトランジスタのソース又はドレインの他方と、前記第2のトランジスタのゲートと、前記第3のトランジスタのソース又はドレインの一方と、前記保持容量の第2の電極と、は電気的に接続され、
前記第3のトランジスタのソース又はドレインの他方は、前記第2の配線と電気的に接続され、
前記第1の配線は、映像信号を伝えることができる機能を有し、
前記第2の配線は、前記第1のトランジスタをオン状態またはオフ状態にすることができる信号を伝えることができる機能を有し、
前記第3の配線は、前記EL素子に電流を伝えることができる機能を有し、
前記第4の配線は、前記第3のトランジスタをオン状態またはオフ状態にすることができる信号を伝えることができる機能を有し、
複数の前記画素は、第1の画素と、第2の画素と、第3の画素と、を有し、
前記第1の画素の前記第3の配線は、第1の電圧を伝えることができる機能を有し、
前記第2の画素の前記第3の配線は、第2の電圧を伝えることができる機能を有し、
前記第3の画素の前記第3の配線は、第3の電圧を伝えることができる機能を有し、
前記第1の画素の前記EL素子は、第1の色を発光することができる機能を有し、
前記第2の画素の前記EL素子は、第2の色を発光することができる機能を有し、
前記第3の画素の前記EL素子は、第3の色を発光することができる機能を有し、
前記第1乃至第3の電圧は互いに異なり、
前記第1乃至第3の色は互いに異なることを特徴とする表示装置。 - 第1のトランジスタのソースまたはドレインの一方に電気的に接続されたソース信号線と、
第1のトランジスタのゲートに電気的に接続されたゲート信号線と、
保持容量の第1の電極と、第2のトランジスタのソース又はドレインの一方と、に電気的に接続された電流供給線と、
第3のトランジスタのゲートに電気的に接続されたリセット信号線と、
前記第2のトランジスタのソース又はドレインの他方に電気的に接続されたEL素子と、を有する画素を複数有し、
前記第1のトランジスタのソース又はドレインの他方と、前記第2のトランジスタのゲートと、前記第3のトランジスタのソース又はドレインの一方と、前記保持容量の第2の電極と、は電気的に接続され、
前記第3のトランジスタのソース又はドレインの他方は、前記ゲート信号線と電気的に接続され、
複数の前記画素は、第1の画素と、第2の画素と、第3の画素と、を有し、
前記第1の画素の前記電流供給線は、第1の電圧を伝えることができる機能を有し、
前記第2の画素の前記電流供給線は、第2の電圧を伝えることができる機能を有し、
前記第3の画素の前記電流供給線は、第3の電圧を伝えることができる機能を有し、
前記第1の画素の前記EL素子は、第1の色を発光することができる機能を有し、
前記第2の画素の前記EL素子は、第2の色を発光することができる機能を有し、
前記第3の画素の前記EL素子は、第3の色を発光することができる機能を有し、
前記第1乃至第3の電圧は互いに異なり、
前記第1乃至第3の色は互いに異なることを特徴とする表示装置。 - 請求項12において、
前記第1の電圧は、前記第2の電圧及び前記第3の電圧よりも高く、
前記第2の配線は、前記第1の画素の前記第3の配線の電位よりも高い電位を供給することができる機能を有することを特徴とする表示装置。 - 請求項13において、
前記第1の電圧は、前記第2の電圧及び前記第3の電圧よりも高く、
前記ゲート信号線は、前記第1の画素の前記電流供給線の電位よりも高い電位を供給することができる機能を有することを特徴とする表示装置。
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JP2013122619A (ja) | 2013-06-20 |
JP2019040190A (ja) | 2019-03-14 |
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US7113155B2 (en) | 2006-09-26 |
US20090309823A1 (en) | 2009-12-17 |
JP6651587B2 (ja) | 2020-02-19 |
JP2014041354A (ja) | 2014-03-06 |
US8514151B2 (en) | 2013-08-20 |
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JP6291002B2 (ja) | 2018-03-14 |
JP2016105173A (ja) | 2016-06-09 |
JP5712234B2 (ja) | 2015-05-07 |
JP2012053473A (ja) | 2012-03-15 |
JP2018066994A (ja) | 2018-04-26 |
JP2020030415A (ja) | 2020-02-27 |
JP2017111450A (ja) | 2017-06-22 |
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