JP5142138B2 - メモリ・システム内の障害メモリ要素を識別する方法及びメモリ・システム - Google Patents
メモリ・システム内の障害メモリ要素を識別する方法及びメモリ・システム Download PDFInfo
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- JP5142138B2 JP5142138B2 JP2007322378A JP2007322378A JP5142138B2 JP 5142138 B2 JP5142138 B2 JP 5142138B2 JP 2007322378 A JP2007322378 A JP 2007322378A JP 2007322378 A JP2007322378 A JP 2007322378A JP 5142138 B2 JP5142138 B2 JP 5142138B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0409—Online test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
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Description
(1)各シンボル列の列ベクトルは、1次独立である。
(2)任意の2シンボル列の列ベクトルによって張られた空間の次元は、16である。
(3)任意の3シンボル列の列ベクトルによって張られた空間の次元は、24である。
S=H・W t=H・(Vt+E t)=H・Et mod 2
S=Hi・Ei t mod 2)
S1=H1,iEi+H1,jEj (1)
S2=H2,iEi+H2,jEj (2)
S3=H3,iEi+H3,jEj (3)
但し、Ei及びEjは、エラーの大きさであり、非ゼロであると仮定する。集合{1,..,33}に属するkについての比、H2,k/H1,k、H3,k/H2,k 及びH3,k/H1,k は、説明中の復号化機構の鍵である。次の表1は、M1に対するこれらの比を明示的に示す。
H3,r/H2,r は、H3,s/H2,s とは異なる。
H2,r/H1,r は、H2,s/H1,s とは異なる。
H3,r/H1,r は、H3,s/H1,s とは異なる。
このことは、前述の表を直接調べれば、理解することができる。
i=34であると仮定すると、Hi,2=Hi,3=0となるから、前述の式(1)〜(3)は、次のように変換される。
S1=Ei+H1,jEj (4)
S2=H2,jEj (5)
S3=H3,jEj (6)
j=35であれば、S3=0及びS2=Ej となり、j=36であれば、S2=0及びS3=Ej となる。他方、jが集合{1,..,33}に属するのであれば、S2 又はS3 の何れも、ゼロに等しくなり得ない(なぜなら、H2,j 及びH3,j は、両方とも非ゼロであるからである)。S2 とH3,j/H2,j とを乗算すると、S3 が得られる。さらに、集合{1,..,33}に属するがjと等しくない、他の任意のkについて、H3,k/H2,k は、H3,j/H2,j とは異なる(これは、本セクションの冒頭で観察したことである)。従って、図10に示す回路は、i=34である場合の特定の状況において、jの値を検出するであろう(この回路では、Lj=0を除いて、全ての出力信号Lxは1に等しいから、一致(==)回路は、これが真であれば0を与え、さもなければ1を与える)。jの値を検出すると、エラーの大きさEi、Ejを計算しなければならない。 図11は、これらを計算するための回路を示す。i=35及びi=36であるケースについても、同様の構成を設計することができる。
(仮定により非ゼロである)H1,i、H2,i 及びH3,i を分割すると、次式に示すような結果が得られる。
S1/H1,i=Ei+(H1,j/H1,i)Ej (7)
S2/H2,i=Ei+(H2,j/H2,i)Ej (8)
S3/H3,i=Ei+(H3,j/H3,i)Ej (9)
この体上の加算演算は、単にXOR演算であり、従って、加算及び減算は同一の演算である。式(7)〜(9)から2つを選び(合計で3つの可能性がある)、選んだ式を加算すると、次式に示すような結果が得られる。
A1+2=S1/H1,i+S2/H2,i=(H1,j/H1,i+H2、j/H2,i)Ej (10)
A2+3=S2/H2,i+S3/H3,i=(H2,j/H2,i+H3,j/H3,i)Ej (11)
A1+3=S1/H1,i+S3/H3,i=(H1,j/H1,i+H3,j/H3,i)Ej (12)
jが集合{34,35,36}に属するのであれば、前式の1つだけがゼロになるであろう。さらに、jが集合{1,..,33}に属するのであれば、A1+2、A2+3、A1+3 のどれもゼロに等しくなり得ない。これは、本セクションの初めにH行列から導いた特性から理解することができる。 j=34であると仮定すると、H2,j=H3,j=0となり、従ってA2+3=0となる。さらに、A1+2=A1+3=Ej/H1,iとなる。j=35及びj=36について同様の分析を行うと、次の表に示す結果が得られる。
H2,k H3,k=T56(H1,k)2
H3,i 及びH3,j を置き換えるためにこの関係を使用して比A2+3/A1+2 を形成し、その結果を簡約化すると、次式が得られる。
H1,j/H2,j=(A2+3/A1+2+1)(H1,i/H2,i)
(H1,j/H2,j)A1+2=(A1+2+A2+3)(H1,i/H2,i)
この関係が成立するjの一意的な値を検出するために、集合{1,..,33}に属する全てのインデックスkについて、積(H1k/H2k)A1+2 が列に形成された後、右辺と一致するか否かを検査することが行われる。因子(H1,i/H2,i)は、ハードワイヤされた入力及び選択子iを有する、マルチプレクサを使用することによって得られる。
Claims (20)
- 読み取り要求に応答して2つ以上のメモリ・モジュールが一斉に動作するメモリ・システム内の障害メモリ要素を識別する方法であって、
記憶アドレスにおけるエラーが訂正不能エラー(UE)であることに応じて、当該訂正不能エラー(UE)に関連付けられたシンドローム・ビット及びアドレスを受信するステップと、
以前の訂正可能エラー(CE)が前記訂正不能エラー(UE)と同じアドレス・レンジで生じていることに応答して、
メモリ装置の位置を指定する前記以前のCEのロケーション及び、前記UEに関連付けられた前記シンドローム・ビットを入力として使用することにより、メモリ装置の位置を指定する前記UEのロケーションを決定するステップと、
前記UEの前記ロケーションに関連付けられた障害メモリ要素を識別するステップと
を含む、前記方法。 - 記憶アドレスにおけるエラーを検出するステップと、
前記検出したエラーが訂正可能エラーであるかどうか判断するステップと
を含み、
前記検出したエラーが訂正可能エラーでないこと、すなわち前記検出したエラーが訂正不能エラー(UE)であることに応じて、前記受信するステップが実行される、請求項1に記載の方法。 - 前記障害メモリ要素がメモリ装置及びメモリ・モジュールのうちの1つ以上である、請求項1又は2に記載の方法。
- 前記UEの前記ロケーションで読み取られたデータを訂正するステップをさらに含む、請求項1〜3のいずれか一項に記載の方法。
- 前記受信するステップ、前記決定するステップ及び前記識別するステップのうちの1つ以上がサービス・プロセッサによって実行される、請求項1〜4のいずれか一項に記載の方法。
- 前記以前のCEの前記ロケーションが不揮発性記憶装置から検索される、請求項1〜5のいずれか一項に記載の方法。
- 前記障害メモリ要素を識別する視覚的な標識を活性化するステップ及び前記障害メモリ要素を指示する報告を生成するステップのうちの1つ以上を実行することをさらに含む、請求項1〜6のいずれか一項に記載の方法。
- 前記以前のCE及び前記UEの一方又は両方の大きさを決定するステップをさらに含む、請求項1〜7のいずれか一項に記載の方法。
- 前記シンドローム・ビットが単一シンボル・エラー訂正−2重シンボル・エラー検出符号から生成される、請求項1〜8のいずれか一項に記載の方法。
- 読み取り要求に応答して2つ以上のメモリ・モジュールが一斉に動作するメモリ・システム内の障害メモリ要素を識別する方法であって、
記憶アドレスにおけるエラーが訂正不能エラー(UE)であることに応じて、当該訂正不能エラー(UE)に関連付けられたアドレス、並びに当該UEに関係する1つ以上のシンドローム・ビット及び読み取りデータを含むデータを受信するステップと、
以前の訂正可能エラー(CE)が前記訂正不能エラー(UE)と同じアドレス・レンジで生じていることに応答して、
メモリ装置の位置を指定する前記以前のCEに関係する前記読み取りデータ及び、前記UEに関係する前記データを入力として使用することにより、障害メモリ要素を識別するステップと
を含む、前記方法。 - 前記障害メモリ要素がメモリ装置及びメモリ・モジュールのうちの1つ以上である、請求項10に記載の方法。
- 前記UEに関係する前記読み取りデータを訂正するステップをさらに含む、請求項10又は11に記載の方法。
- 前記受信するステップ、及び前記識別するステップのうちの1つ以上がサービス・プロセッサによって実行される、請求項10〜12のいずれか一項に記載の方法。
- 前記以前のCEのロケーションが不揮発性記憶装置から検索される、請求項10〜13のいずれか一項に記載の方法。
- 前記障害メモリ要素を識別する視覚的な標識を活性化するステップ及び前記障害メモリ要素を指示する報告を生成するステップのうちの1つ以上を実行することをさらに含む、請求項10〜14のいずれか一項に記載の方法。
- 前記シンドローム・ビットが単一シンボル・エラー訂正−2重シンボル・エラー検出符号から生成される、請求項10〜15のいずれか一項に記載の方法。
- 障害メモリ要素を識別するためのメモリ・システムであって、
読み取り要求に応答して一斉に動作する2つ以上のメモリ・モジュールであって、前記メモリ・モジュールの各々は1つ以上のメモリ装置を含む、前記メモリ・モジュールと、
一のアドレスにおける第1の障害に関連付けられた障害情報を格納するための記憶手段と、
論理を含むプロセッサと
を備えており、
前記論理が、
記憶アドレスにおけるエラーが訂正不能エラー(UE)であることに応じて、当該訂正不能エラー(UE)に関連付けられたシンドローム・ビット及びアドレスを受信し、
以前の訂正可能エラー(CE)が前記訂正不能エラー(UE)と同じアドレス・レンジで生じていることに応答して、
メモリ装置の位置を指定する前記以前のCEの前記ロケーション及び、前記UEに関連付けられた前記シンドローム・ビットを入力として使用することにより、メモリ装置の位置を指定する前記UEのロケーションを決定し、
前記UEの前記ロケーションに関連付けられた障害メモリ要素を識別するように構成されている、
前記メモリ・システム。 - 前記論理がハードウェア及びソフトウェアのうちの1つ以上で実装される、 請求項17に記載のメモリ・システム。
- 前記論理が前記UEの前記ロケーションで読み取られたデータを訂正する動作をさらに実行するように構成されている、請求項17又は18に記載のメモリ・システム。
- 前記シンドローム・ビットが単一シンボル・エラー訂正−2重シンボル・エラー検出符号から生成される、請求項17〜19のいずれか一項に記載のメモリ・システム。
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US11/619038 | 2007-01-02 | ||
US11/619,038 US7721140B2 (en) | 2007-01-02 | 2007-01-02 | Systems and methods for improving serviceability of a memory system |
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US7877666B2 (en) * | 2006-12-30 | 2011-01-25 | Intel Corporation | Tracking health of integrated circuit structures |
US8041989B2 (en) * | 2007-06-28 | 2011-10-18 | International Business Machines Corporation | System and method for providing a high fault tolerant memory system |
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2007
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- 2007-12-13 JP JP2007322378A patent/JP5142138B2/ja not_active Expired - Fee Related
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CN101217060A (zh) | 2008-07-09 |
CN101217060B (zh) | 2012-03-14 |
JP2008165772A (ja) | 2008-07-17 |
US20080162991A1 (en) | 2008-07-03 |
US7721140B2 (en) | 2010-05-18 |
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