JP5088465B2 - 不揮発性半導体メモリ - Google Patents
不揮発性半導体メモリ Download PDFInfo
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- JP5088465B2 JP5088465B2 JP2006191470A JP2006191470A JP5088465B2 JP 5088465 B2 JP5088465 B2 JP 5088465B2 JP 2006191470 A JP2006191470 A JP 2006191470A JP 2006191470 A JP2006191470 A JP 2006191470A JP 5088465 B2 JP5088465 B2 JP 5088465B2
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- 239000004065 semiconductor Substances 0.000 title description 61
- 230000015654 memory Effects 0.000 claims description 117
- 238000003860 storage Methods 0.000 claims description 42
- 239000002184 metal Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 12
- 239000011159 matrix material Substances 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 97
- 238000000034 method Methods 0.000 description 76
- 238000004519 manufacturing process Methods 0.000 description 58
- 238000009792 diffusion process Methods 0.000 description 52
- 230000007423 decrease Effects 0.000 description 8
- 239000002784 hot electron Substances 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 3
- 240000004050 Pentaglottis sempervirens Species 0.000 description 2
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7889—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Description
前記行列の列方向に整列したメモリトランジスタのソース領域を相互に接続するよう列方向に配線された複数の第1次ソース線と、
前記列方向に整列したメモリトランジスタのドレイン領域を相互に接続するよう、前記第1次ソース線とは異なる層において列方向に配線された複数の平行なビット線と、
前記列方向に実質的に直交する行方向に整列したメモリトランジスタのゲートを相互に接続するよう行方向に配線された線をゲート線とし、
前記行列のp行(p<n)置きに1行ずつ配線される第2次ソース線であって、前記第1次ソース線を相互に接続するメタルで形成された第2次ソース線と、
を含んでいる不揮発性半導体メモリが提供される。
前記行列の行および列の方向にそれぞれ整列したメモリトランジスタのソース領域を相互に接続するように配線された第1の共通拡散ソース線と、
前記列方向に整列したメモリトランジスタのドレイン領域を相互に接続するよう、前記第1の共通拡散ソース線とは異なる層において列方向に配線された複数の平行なビット線と、
前記列方向に実質的に直交する行方向に整列したメモリトランジスタのゲートを相互に接続するよう行方向に配線された線をゲート線とし、
前記ソース面に接続されるメタルで形成された第2次ソース線であって、前記行列のp行(p<n)置きに1行ずつ配線される第2次ソース線と、
を含んでいる不揮発性半導体メモリが提供される。
選択したビット線に0Vまたは正の第一電圧を印加し、非選択のビット線に0Vを印加し、選択したゲート線に正の第二電圧を印加し、非選択のゲート線に0Vを印加し、第1次ソース線または第1の共通拡散ソース線と第2次ソース線に0Vを印加することで、選択したメモリトランジスタにホット・エレクトロンを利用して電荷蓄積層へ電荷の注入を行う、不揮発性半導体メモリへの書き込み方法が提供される。
選択したゲート線に正の第一電圧を印加し、非選択のゲート線に、0Vを印加し、第1次ソース線または第1の共通拡散ソース線と第2次ソース線に0Vを印加し、選択したビット線に正の第二電圧を印加することで、選択したメモリトランジスタを読み出す、不揮発性半導体メモリからの読み出し方法が提供される。
ビット線と第1次ソース線または第1の共通拡散ソース線と第2次ソース線に正の第一電圧を印加し、ゲート線に0Vを印加することで、FN(Fowler-Nordheim)トンネル電流を利用して全メモリトランジスタの電荷蓄積層から電荷を放出する、不揮発性半導体メモリの消去方法が提供される。
ビット線と第1次ソース線または第1の共通拡散ソース線と第2次ソース線に正の第一電圧を印加し、選択したゲート線に0Vを印加し、非選択のゲート線に正の第二電圧を印加することで、FNトンネル電流を利用して選択したゲート線に接続されたメモリトランジスタの電荷蓄積層から電荷を放出する、不揮発性半導体メモリの消去方法が提供される。
2 第1次ソース線(1stSL)
3 ソース拡散層
4 島状半導体層
5 ドレイン拡散層
6 電荷蓄積層
7 ゲート線(WL)
8 ビット線
9 第2次ソース線(2ndSL)
10 第1の共通拡散ソース線
100 P型シリコン
101 島状半導体層
102 トンネル絶縁膜
103 多結晶シリコン膜
104 インターポリ絶縁膜
105 多結晶シリコン膜
106 レジスト
107 層間絶縁膜
108 メタル
109 層間絶縁膜
200 選択したビット線
201 非選択のビット線
202 選択したゲート線
203 非選択のゲート線
204 第1次ソース線
205 第2次ソース線
300 電荷蓄積層
301 粒子状電荷蓄積層
Claims (4)
- ソース領域、チャネル領域及びドレイン領域が基板側からこの順に形成され、前記チャネル領域の外側に電荷蓄積層を有する不揮発性メモリトランジスタが前記基板上に行列状に配置され、行方向に配置されたメモリトランジスタのゲートに接続する各行ごとにメモリトランジスタ選択線が配置され、列方向に配置されたメモリトランジスタのソースに接続する各列ごとに第1次ソース線が配置され、複数の第1次ソース線に接続する行方向に配置される第2次ソース線がメタルであることを特徴とする不揮発性メモリ。
- 少なくとも、請求項1の不揮発性メモリが列方向に複数配列した不揮発性メモリ。
- 少なくとも、請求項1の不揮発性メモリが行方向に複数配列した不揮発性メモリ。
- 少なくとも、請求項1の不揮発性メモリが列方向及び行方向に複数配列した不揮発性メモリ。
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006191470A JP5088465B2 (ja) | 2006-07-12 | 2006-07-12 | 不揮発性半導体メモリ |
TW096125164A TW200814068A (en) | 2006-07-12 | 2007-07-11 | Nonvolatile semiconductor memory and activation method thereof |
KR1020097000601A KR101020846B1 (ko) | 2006-07-12 | 2007-07-12 | 비휘발성 반도체 메모리 및 그 구동방법 |
EP07790683A EP2043145A4 (en) | 2006-07-12 | 2007-07-12 | NON-VOLATILE SEMICONDUCTOR MEMORY AND CORRESPONDING DRIVE METHOD |
EP13170935.4A EP2639825A3 (en) | 2006-07-12 | 2007-07-12 | Nonvolatile semiconductor memory and method of driving the same |
PCT/JP2007/063889 WO2008007731A1 (en) | 2006-07-12 | 2007-07-12 | Nonvolatile semiconductor memory and its drive method |
CN2007800262290A CN101490837B (zh) | 2006-07-12 | 2007-07-12 | 非易失性半导体存储器及其驱动方法 |
US12/319,782 US7940574B2 (en) | 2006-07-12 | 2009-01-12 | Nonvolatile semiconductor memory and method of driving the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006191470A JP5088465B2 (ja) | 2006-07-12 | 2006-07-12 | 不揮発性半導体メモリ |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008021782A JP2008021782A (ja) | 2008-01-31 |
JP2008021782A5 JP2008021782A5 (ja) | 2010-11-25 |
JP5088465B2 true JP5088465B2 (ja) | 2012-12-05 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006191470A Active JP5088465B2 (ja) | 2006-07-12 | 2006-07-12 | 不揮発性半導体メモリ |
Country Status (7)
Country | Link |
---|---|
US (1) | US7940574B2 (ja) |
EP (2) | EP2639825A3 (ja) |
JP (1) | JP5088465B2 (ja) |
KR (1) | KR101020846B1 (ja) |
CN (1) | CN101490837B (ja) |
TW (1) | TW200814068A (ja) |
WO (1) | WO2008007731A1 (ja) |
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US9041092B2 (en) * | 2012-09-07 | 2015-05-26 | Unisantis Electronics Singapore Pte. Ltd. | Semiconductor device and method for producing the same |
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CN109326604A (zh) * | 2017-08-01 | 2019-02-12 | 华邦电子股份有限公司 | 三维存储器及其操作方法 |
KR20230012697A (ko) * | 2021-07-16 | 2023-01-26 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치에 데이터를 삭제하기 위한 장치 및 방법 |
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JP2005191489A (ja) * | 2003-12-26 | 2005-07-14 | Sharp Corp | 半導体記憶装置およびその製造方法 |
JP2005268418A (ja) * | 2004-03-17 | 2005-09-29 | Fujio Masuoka | 半導体記憶装置及びその製造方法 |
JP4331053B2 (ja) | 2004-05-27 | 2009-09-16 | 株式会社東芝 | 半導体記憶装置 |
JP2005260253A (ja) * | 2005-04-04 | 2005-09-22 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
US8159870B2 (en) * | 2008-04-04 | 2012-04-17 | Qualcomm Incorporated | Array structural design of magnetoresistive random access memory (MRAM) bit cells |
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TW200814068A (en) | 2008-03-16 |
KR20090031416A (ko) | 2009-03-25 |
US7940574B2 (en) | 2011-05-10 |
EP2639825A3 (en) | 2013-10-16 |
KR101020846B1 (ko) | 2011-03-09 |
CN101490837B (zh) | 2010-09-29 |
EP2043145A1 (en) | 2009-04-01 |
US20090129171A1 (en) | 2009-05-21 |
WO2008007731A1 (en) | 2008-01-17 |
EP2639825A2 (en) | 2013-09-18 |
EP2043145A4 (en) | 2010-11-10 |
JP2008021782A (ja) | 2008-01-31 |
CN101490837A (zh) | 2009-07-22 |
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