JP4789308B2 - 半導体装置のテスト電源供給回路 - Google Patents

半導体装置のテスト電源供給回路 Download PDF

Info

Publication number
JP4789308B2
JP4789308B2 JP2000191022A JP2000191022A JP4789308B2 JP 4789308 B2 JP4789308 B2 JP 4789308B2 JP 2000191022 A JP2000191022 A JP 2000191022A JP 2000191022 A JP2000191022 A JP 2000191022A JP 4789308 B2 JP4789308 B2 JP 4789308B2
Authority
JP
Japan
Prior art keywords
power supply
test
supply voltage
semiconductor device
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000191022A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001056360A (ja
Inventor
奇 煥 崔
▲ヤン▼ 湖 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2001056360A publication Critical patent/JP2001056360A/ja
Application granted granted Critical
Publication of JP4789308B2 publication Critical patent/JP4789308B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2000191022A 1999-07-02 2000-06-26 半導体装置のテスト電源供給回路 Expired - Fee Related JP4789308B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019990026594A KR100343283B1 (ko) 1999-07-02 1999-07-02 반도체 장치의 테스트 전원 공급 회로
KR1999P-26594 1999-07-02

Publications (2)

Publication Number Publication Date
JP2001056360A JP2001056360A (ja) 2001-02-27
JP4789308B2 true JP4789308B2 (ja) 2011-10-12

Family

ID=19598986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000191022A Expired - Fee Related JP4789308B2 (ja) 1999-07-02 2000-06-26 半導体装置のテスト電源供給回路

Country Status (3)

Country Link
US (2) US6483759B1 (ko)
JP (1) JP4789308B2 (ko)
KR (1) KR100343283B1 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6649932B2 (en) * 2002-04-01 2003-11-18 Micrel, Inc. Electrical print resolution test die
JP2005302809A (ja) * 2004-04-07 2005-10-27 Toshiba Corp 半導体装置
US7145347B2 (en) * 2004-08-31 2006-12-05 International Business Machines Corporation Method and apparatus for measuring transfer characteristics of a semiconductor device
US7154285B2 (en) * 2004-09-30 2006-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for providing PCB layout for probe card
US20100033204A1 (en) * 2006-09-26 2010-02-11 Takeshi Santo Semiconductor inspection apparatus and semiconductor integrated circuit
JP2008122362A (ja) * 2006-10-20 2008-05-29 Matsushita Electric Ind Co Ltd 半導体検査装置および半導体検査手法
KR100962678B1 (ko) * 2007-07-04 2010-06-11 삼성전자주식회사 듀얼 미러 칩을 포함하는 웨이퍼 및 상기 칩을 포함하는 멀티칩 패키지
JP5329116B2 (ja) * 2008-04-04 2013-10-30 ルネサスエレクトロニクス株式会社 表示装置用駆動回路、テスト回路、及びテスト方法
US20090267179A1 (en) * 2008-04-24 2009-10-29 International Business Machines Corporation System for power performance optimization of multicore processor chip
KR101212723B1 (ko) * 2010-05-31 2012-12-14 에스케이하이닉스 주식회사 반도체 장치
CN105004892A (zh) * 2015-07-31 2015-10-28 佛山市中格威电子有限公司 一种空调功能测试工装
CN107271885A (zh) * 2017-07-05 2017-10-20 西安微电子技术研究所 一种适用于处理器类器件的单粒子试验***

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4835458A (en) * 1987-11-09 1989-05-30 Intel Corporation Signature analysis technique for defect characterization of CMOS static RAM cell failures
KR950014099B1 (ko) * 1992-06-12 1995-11-21 가부시기가이샤 도시바 반도체 기억장치
US5467024A (en) * 1993-11-01 1995-11-14 Motorola, Inc. Integrated circuit test with programmable source for both AC and DC modes of operation
JP2710574B2 (ja) * 1994-12-28 1998-02-10 山形日本電気株式会社 プリスケーラｉｃテスト方法及びテストプローブカード
US5808947A (en) * 1995-08-21 1998-09-15 Sgs-Thomson Microelectronics, Inc. Integrated circuit that supports and method for wafer-level testing
US6078173A (en) * 1996-04-08 2000-06-20 General Electric Company Simultaneous self test of multiple inverters in an AC motor system
JP3123444B2 (ja) * 1996-09-27 2001-01-09 安藤電気株式会社 Ｉｃ試験装置
US6239604B1 (en) * 1996-10-04 2001-05-29 U.S. Philips Corporation Method for inspecting an integrated circuit by measuring a voltage drop in a supply line of sub-circuit thereof
US6326801B1 (en) * 1996-10-31 2001-12-04 Texas Instruments Incorporated Wafer of semiconductor material with dies, probe areas and leads
US6119255A (en) * 1998-01-21 2000-09-12 Micron Technology, Inc. Testing system for evaluating integrated circuits, a burn-in testing system, and a method for testing an integrated circuit
US6031755A (en) * 1998-03-25 2000-02-29 Rohm Co., Ltd. Non-volatile semiconductor memory device and its testing method
JP2000021938A (ja) * 1998-06-29 2000-01-21 Mitsubishi Electric Corp 半導体ウェハ、及び半導体装置の検査方法

Also Published As

Publication number Publication date
JP2001056360A (ja) 2001-02-27
KR20010008668A (ko) 2001-02-05
KR100343283B1 (ko) 2002-07-15
US6492832B2 (en) 2002-12-10
US6483759B1 (en) 2002-11-19
US20020149983A1 (en) 2002-10-17

Similar Documents

Publication Publication Date Title
US7170091B2 (en) Probe look ahead: testing parts not currently under a probehead
KR100400952B1 (ko) 집적 회로 모듈내의 집적 회로 다이를 검사하기 위한 장치 및 방법
US6815971B2 (en) Method and apparatus for stress testing integrated circuits using an adjustable AC hot carrier injection source
KR100466984B1 (ko) 테스트 소자 그룹 회로를 포함하는 집적 회로 칩 및 그것의 테스트 방법
US6026039A (en) Parallel test circuit for semiconductor memory
JP4789308B2 (ja) 半導体装置のテスト電源供給回路
US7995408B2 (en) Circuit for supplying a reference voltage in a semiconductor memory device for testing an internal voltage generator therein
US20100013510A1 (en) Systems and methods for defect testing of externally accessible integrated circuit interconnects
US5898700A (en) Test signal generator and method for testing a semiconductor wafer having a plurality of memory chips
JP2000011684A (ja) 入力保護回路、アンチフューズアドレス検出回路および半導体集積回路装置
JP2007287770A (ja) 半導体集積回路
US7202692B2 (en) Semiconductor chip and method of testing the same
US8624615B2 (en) Isolation circuit
US7134059B2 (en) Pad connection structure of embedded memory devices and related memory testing method
JP2005072375A (ja) 半導体集積回路
US7079433B1 (en) Wafer level burn-in of SRAM
US6819161B2 (en) Structure for temporarily isolating a die from a common conductor to facilitate wafer level testing
US7251772B2 (en) Circuit arrangement having a number of integrated circuit components on a carrier substrate and method for testing a circuit arrangement of this type
JP3783865B2 (ja) 半導体装置及びそのバーンインテスト方法、製造方法並びにバーンインテスト制御回路
KR100465541B1 (ko) 멀티 프로빙 패드를 구비한 반도체 테스트 장치
JP2954076B2 (ja) 半導体集積回路ウェハ及びその試験方法
JPH1078474A (ja) 半導体装置およびその製造方法
JP2000286316A (ja) 半導体装置
US20110291681A1 (en) Semiconductor apparatus
JPH05211214A (ja) Ｉｃマーキング回路

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070322

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100622

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100917

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110628

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110719

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140729

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees