JP2018032830A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2018032830A JP2018032830A JP2016166213A JP2016166213A JP2018032830A JP 2018032830 A JP2018032830 A JP 2018032830A JP 2016166213 A JP2016166213 A JP 2016166213A JP 2016166213 A JP2016166213 A JP 2016166213A JP 2018032830 A JP2018032830 A JP 2018032830A
- Authority
- JP
- Japan
- Prior art keywords
- bonding layer
- semiconductor element
- semiconductor device
- layer
- peripheral surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/29076—Plural core members being mutually engaged together, e.g. through inserts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/29078—Plural core members being disposed next to each other, e.g. side-to-side arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
Landscapes
- Die Bonding (AREA)
Abstract
Description
10 :リードフレーム
12 :外側接合層
12a :外周面
12b :内周面
14 :内側接合層
16 :接合層
18 :半導体素子
100 :アクティブ領域
100a :発熱領域
110 :非アクティブ領域
114 :ペースト層
120 :境界
Claims (1)
- 金属板に接合層を介して半導体素子を接合した半導体装置であって、
前記接合層は、前記接合層の外周面を規定する外側接合層と、前記外側接合層の内側を充填する内側接合層を備えており、
前記外側接合層は、前記内側接合層よりも熱伝導率と熱膨張率が低く、
前記外側接合層の内面と外面が、前記金属板に近づくにつれて、前記外側接合層の外側に向けて傾斜していることを特徴とする、
半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016166213A JP2018032830A (ja) | 2016-08-26 | 2016-08-26 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016166213A JP2018032830A (ja) | 2016-08-26 | 2016-08-26 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2018032830A true JP2018032830A (ja) | 2018-03-01 |
Family
ID=61303558
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016166213A Pending JP2018032830A (ja) | 2016-08-26 | 2016-08-26 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2018032830A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022124895A2 (en) | 2020-12-08 | 2022-06-16 | Stichting Chip Integration Technology Centre | Integrated circuit comprising improved die attachment layer |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04105333A (ja) * | 1990-08-24 | 1992-04-07 | Nec Corp | 半導体装置 |
JP2005050886A (ja) * | 2003-07-29 | 2005-02-24 | Kyocera Corp | 複合基板及びその製造方法 |
JP2010232388A (ja) * | 2009-03-26 | 2010-10-14 | Panasonic Electric Works Co Ltd | 半導体パッケージ及び半導体部品の実装構造 |
JP2012028433A (ja) * | 2010-07-21 | 2012-02-09 | Nec Network Products Ltd | 電子部品の実装方法 |
JP2012109636A (ja) * | 2012-03-13 | 2012-06-07 | Denso Corp | 電子装置およびその製造方法 |
-
2016
- 2016-08-26 JP JP2016166213A patent/JP2018032830A/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04105333A (ja) * | 1990-08-24 | 1992-04-07 | Nec Corp | 半導体装置 |
JP2005050886A (ja) * | 2003-07-29 | 2005-02-24 | Kyocera Corp | 複合基板及びその製造方法 |
JP2010232388A (ja) * | 2009-03-26 | 2010-10-14 | Panasonic Electric Works Co Ltd | 半導体パッケージ及び半導体部品の実装構造 |
JP2012028433A (ja) * | 2010-07-21 | 2012-02-09 | Nec Network Products Ltd | 電子部品の実装方法 |
JP2012109636A (ja) * | 2012-03-13 | 2012-06-07 | Denso Corp | 電子装置およびその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022124895A2 (en) | 2020-12-08 | 2022-06-16 | Stichting Chip Integration Technology Centre | Integrated circuit comprising improved die attachment layer |
NL2027068B1 (en) * | 2020-12-08 | 2022-07-07 | Stichting Chip Integration Tech Centre | Integrated circuit comprising improved die attachment layer |
WO2022124895A3 (en) * | 2020-12-08 | 2022-09-15 | Stichting Chip Integration Technology Centre | Integrated circuit comprising a substrate, a die and an improved die attachment layer, as well as corresponding method of die bonding |
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