WO2022124895A3 - Integrated circuit comprising a substrate, a die and an improved die attachment layer, as well as corresponding method of die bonding - Google Patents
Integrated circuit comprising a substrate, a die and an improved die attachment layer, as well as corresponding method of die bonding Download PDFInfo
- Publication number
- WO2022124895A3 WO2022124895A3 PCT/NL2021/050747 NL2021050747W WO2022124895A3 WO 2022124895 A3 WO2022124895 A3 WO 2022124895A3 NL 2021050747 W NL2021050747 W NL 2021050747W WO 2022124895 A3 WO2022124895 A3 WO 2022124895A3
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- WIPO (PCT)
- Prior art keywords
- region
- die
- substrate
- thermal expansion
- expansion coefficient
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title abstract 11
- 238000000034 method Methods 0.000 title abstract 2
- 239000000463 material Substances 0.000 abstract 12
- 239000003989 dielectric material Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 239000003822 epoxy resin Substances 0.000 abstract 1
- -1 fibres Substances 0.000 abstract 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 239000002105 nanoparticle Substances 0.000 abstract 1
- 239000002245 particle Substances 0.000 abstract 1
- 229920000647 polyepoxide Polymers 0.000 abstract 1
- 229920000642 polymer Polymers 0.000 abstract 1
- 238000003825 pressing Methods 0.000 abstract 1
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- 229910052709 silver Inorganic materials 0.000 abstract 1
- 239000004332 silver Substances 0.000 abstract 1
- 238000005245 sintering Methods 0.000 abstract 1
Classifications
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
An integrated circuit (IC) (30) is attached to a substrate (10) through an improved die attachment layer (20), whereby an IC-package is formed. The die attachment layer (20) comprises at least one first region (21) comprising a first attachment material and at least one second region (22) comprising a second attachment material different from the first attachment material, wherein the at least one first region (21) is located centrally on the substrate (10), wherein the at least one second region (22) is located eccentrically, such as at a side, at a part of a side, or at a corner, wherein the at least one first region (21) comprises at least one metal (e.g., sintered silver) and the at least one second region (22) comprises a die-attach material selected from heat assisted attach materials, pressure-based attach materials, pressure-less attach materials, thermohardening attach materials, such as epoxy resins, curing attach materials, polymer based attach materials, resin based attach materials, fibres, nanoparticles, and combinations thereof, in particular, wherein the at least one second region (22) comprises particles of dielectric material embedded in a matrix of polymeric material. A thermal expansion coefficient (TCE3) of the at least one first region (21) and a thermal expansion coefficient (TCE4) of the at least one second region (22) may be between a thermal expansion coefficient (TCE1) of the substrate (10) and a thermal expansion coefficient (TCE2) of the die (30). The thermal expansion coefficient (TCE4) of the at least one second region (22) may be between the thermal expansion coefficient (TCE3) of the at least one first region (21) and the thermal expansion coefficient (TCE1) of the substrate (10) or between the thermal expansion coefficient (TCE3) of the at least one first region (21) and the thermal expansion coefficient (TCE2) of the die (30). The elastic modulus (EM1) of the at least one first region (21) may be higher than the elastic modulus (EM2) of the at least one second region (22), wherein, preferably, the elastic modulus (EM1) of the at least one first region (21) is lower than an elastic modulus of the die (30) and wherein, preferably, the elastic modulus (EM2) of the at least one second region (22) is higher than an elastic modulus of the substrate (10), wherein the elastic moduli are each a Young's modulus, a bulk modulus, viscoelastic modulus, and/or a volumetric modulus. The attachment layer (20) may extend up to a side of the die (30), preferably forming a fillet (27). The attachment layer may comprise a cavity (28) for receiving the die (30), preferably a cavity (28) adapted to outer dimensions of the die (30). The die (30) may be a power IC or, alternatively, the integrated circuit may relate to a photonics application, with an improved heat flow from die (30) to the substrate (10), or may relate to an IC requiring precise temperature control thereof, such as a VCSEL circuit. In the manufacturing method, i.e., method of die bonding, the at least one first region (21) may be provided in the form of at least one central bar-shaped volume, optionally with one or more side branches, preferably towards every substrate corner and optionally at each longitudinal side of the substrate (10). The die (30) may be attached to the substrate (10) by applying pressure, by applying heat, by applying curing, by sintering, by diffusion, or by a combination thereof. After attaching the die (30), the first region (21) is spread out over the central region of the substrate (10), whereas the second regions (22) are slightly increased in surface are size and are positioned at the sides and corners.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL2027068A NL2027068B1 (en) | 2020-12-08 | 2020-12-08 | Integrated circuit comprising improved die attachment layer |
NL2027068 | 2020-12-08 |
Publications (2)
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WO2022124895A2 WO2022124895A2 (en) | 2022-06-16 |
WO2022124895A3 true WO2022124895A3 (en) | 2022-09-15 |
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PCT/NL2021/050747 WO2022124895A2 (en) | 2020-12-08 | 2021-12-08 | Integrated circuit comprising improved die attachment layer |
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WO (1) | WO2022124895A2 (en) |
Citations (8)
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EP0712153A2 (en) * | 1994-11-10 | 1996-05-15 | Vlt Corporation | Packaging electrical circuits |
US20130256894A1 (en) * | 2012-03-29 | 2013-10-03 | International Rectifier Corporation | Porous Metallic Film as Die Attach and Interconnect |
US20150014865A1 (en) * | 2012-02-09 | 2015-01-15 | Robert Bosch Gmbh | Connection arrangement of an electric and/or electronic component |
DE102013226334A1 (en) * | 2013-12-18 | 2015-06-18 | Robert Bosch Gmbh | Circuit carrier with a sintered semiconductor device |
JP2015185559A (en) * | 2014-03-20 | 2015-10-22 | 三菱電機株式会社 | Method of manufacturing semiconductor module, and semiconductor module |
JP2018032830A (en) * | 2016-08-26 | 2018-03-01 | トヨタ自動車株式会社 | Semiconductor device |
US20180204786A1 (en) * | 2017-01-18 | 2018-07-19 | Stmicroelectronics, Inc. | Die with metallized sidewall and method of manufacturing |
US20190006268A1 (en) * | 2017-06-29 | 2019-01-03 | Renesas Electronics Corporation | Manufacturing method for semiconductor device and semiconductor device |
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2020
- 2020-12-08 NL NL2027068A patent/NL2027068B1/en active
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2021
- 2021-12-08 WO PCT/NL2021/050747 patent/WO2022124895A2/en active Application Filing
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EP0712153A2 (en) * | 1994-11-10 | 1996-05-15 | Vlt Corporation | Packaging electrical circuits |
US20150014865A1 (en) * | 2012-02-09 | 2015-01-15 | Robert Bosch Gmbh | Connection arrangement of an electric and/or electronic component |
US20130256894A1 (en) * | 2012-03-29 | 2013-10-03 | International Rectifier Corporation | Porous Metallic Film as Die Attach and Interconnect |
DE102013226334A1 (en) * | 2013-12-18 | 2015-06-18 | Robert Bosch Gmbh | Circuit carrier with a sintered semiconductor device |
JP2015185559A (en) * | 2014-03-20 | 2015-10-22 | 三菱電機株式会社 | Method of manufacturing semiconductor module, and semiconductor module |
JP2018032830A (en) * | 2016-08-26 | 2018-03-01 | トヨタ自動車株式会社 | Semiconductor device |
US20180204786A1 (en) * | 2017-01-18 | 2018-07-19 | Stmicroelectronics, Inc. | Die with metallized sidewall and method of manufacturing |
US20190006268A1 (en) * | 2017-06-29 | 2019-01-03 | Renesas Electronics Corporation | Manufacturing method for semiconductor device and semiconductor device |
Non-Patent Citations (3)
Title |
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-: "DuPont(TM) Kapton(TM) KA802", 14 May 2021 (2021-05-14), XP055944162, Retrieved from the Internet <URL:https://web.archive.org/web/20210514222238/https://insulectro-pe.com/products/dupont(TM)-kapton(TM)-ka802> [retrieved on 20220719] * |
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NL2027068B1 (en) | 2022-07-07 |
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