JP2014120773A - パッケージ構造及びパッケージ方法 - Google Patents
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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Abstract
【解決手段】表面に形成された複数のベアチップパッドを有するICベアチップと、第一面に形成された複数の第一パッドと第二面に形成された複数の第二パッドとを有するフレキシブルパッケージ基板と、フレキシブルパッケージ基板の第一面に形成され、異なる高さをそれぞれ有し、第一パッドにそれぞれ対応し、且つベアチップパッドと接触し、ICベアチップをパッケージする複数のスタッドと、複数の接点パッドを有する回路板であって、フレキシブルパッケージ基板の第二パッドはそれぞれ半田により接点パッドと接触することで接合する回路板とを備えるパッケージ構造及びパッケージ方法である。パッケージ基板、回路板に極めて低い応力のみが発生することができ、応力によるスタッド、半田の接合破断、及び、スタッド、半田によるはんだぬれ不良、コールドはんだ接合という問題を解決する。
【選択図】図3
Description
表面に形成された複数のベアチップパッドを有するICベアチップを提供する工程と、
第一面に形成された複数の第一パッドと第二面に形成された複数の第二パッドとを有するフレキシブルパッケージ基板を提供する工程と、
異なる高さをそれぞれ有する複数のスタッドを前記フレキシブルパッケージ基板の前記第一面に形成する工程と、
前記ICベアチップのこれらのベアチップパッドを有する前記表面を前記フレキシブルパッケージ基板の前記第一面に向かわせ、これらのベアチップパッドをそれぞれこれらのスタッドに接合させたる工程と、を含むパッケージ方法を提供する。そして、本発明のパッケージ構造では、フレキシブルパッケージ基板の前記第一面が不平坦である。
を備える。
11 第1パッド
12 エポキシ樹脂
2 スタッド
3 硬質多層パッケージ基板
31 第2パッド
32 第3パッド
4 硬質プリント回路板
41 電気的な接続接点
5 半田
6 エポキシ樹脂
100 ICベアチップ
150 ベアチップパッド
200 フレキシブルパッケージ基板
251 第一パッド
252 第二パッド
300 回路板
350 接点パッド
400 スタッド
500 半田
Claims (9)
- パッケージ構造であって、表面に形成された複数のベアチップパッドを有するICベアチップと、
第一面に形成された複数の第一パッドと第二面に形成された複数の第二パッドとを有するフレキシブルパッケージ基板と、
前記フレキシブルパッケージ基板の前記第一面に形成され、異なる高さをそれぞれ有し、これらの第一パッドにそれぞれ対応する複数のスタッドであって、前記フレキシブルパッケージ基板の前記第一面に接合したこれらのスタッドはそれぞれこれらのベアチップパッドと接合し、前記ICベアチップをパッケージするために用いられる複数のスタッドとを備えることを特徴とするパッケージ構造。 - 前記第一面に形成されたこれらの第一パッドのうち、少なくとも一つのパッドは他のパッドと面一にならないことを特徴とする請求項1に記載のパッケージ構造。
- 複数の接点パッドを有する回路板であって、前記フレキシブルパッケージ基板の前記第二面に形成されたこれらの第二パッドはそれぞれ半田によりこれらの接点パッドと接合する回路板を更に備えることを特徴とする請求項1に記載のパッケージ構造。
- これらのスタッドがこれらの第一パッドと寄りの幅は、これらのスタッドがこれらのベアチップパッドと寄りの幅より大きい請求項1に記載のパッケージ構造。
- パッケージ方法であって、表面に形成された複数のベアチップパッドを有するICベアチップを提供する工程と、
第一面に形成された複数の第一パッドと第二面に形成された複数の第二パッドとを有するフレキシブルパッケージ基板を提供する工程と、
異なる高さをそれぞれ有する複数のスタッドを前記フレキシブルパッケージ基板の前記第一面に形成する工程と、
前記ICベアチップのこれらのベアチップパッドを有する前記表面を前記フレキシブルパッケージ基板の前記第一面に向かわせ、加圧又は加熱を実施し、これらのベアチップパッドをそれぞれこれらのスタッドに接合させる工程とを含むことを特徴とするパッケージ方法。 - 前記第一面に形成されたこれらの第一パッドのうち、少なくとも一つのパッドは他のパッドと面一にならないことを特徴とする請求項5に記載のパッケージ方法。
- 前記加圧又は加熱の工程の後に、それぞれこれらの第二パッド上に半田を形成する工程を更に含むことを特徴とする請求項5に記載のパッケージ方法。
- 前記フレキシブルパッケージ基板を提供する工程の前に、前記フレキシブルパッケージ基板をキャリアプレートステージから分離する工程を更に含むことを特徴とする請求項5に記載のパッケージ方法。
- 半田を形成する工程の後に、複数の接点パッドを有する回路板を提供し、加圧又は加熱を実施し、前記回路板のこれらの接点パッドと前記フレキシブルパッケージ基板のこれらの半田をの接合する工程を更に含むことを特徴とする請求項7に記載のパッケージ方法。
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US (1) | US20140167255A1 (ja) |
EP (1) | EP2750186A3 (ja) |
JP (1) | JP2014120773A (ja) |
KR (1) | KR20140078541A (ja) |
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Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9385098B2 (en) * | 2012-11-21 | 2016-07-05 | Nvidia Corporation | Variable-size solder bump structures for integrated circuit packaging |
US9679862B2 (en) * | 2014-11-28 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device having conductive bumps of varying heights |
WO2017039583A1 (en) * | 2015-08-28 | 2017-03-09 | Intel Corporation | Use of sacrificial material to compensate for thickness variation in microelectronic substrates |
US10121759B2 (en) * | 2015-11-04 | 2018-11-06 | Kulicke And Soffa Industries, Inc. | On-bonder automatic overhang die optimization tool for wire bonding and related methods |
CN106971945B (zh) * | 2016-01-14 | 2021-01-22 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
CN107424966B (zh) * | 2017-06-30 | 2019-07-12 | 永道无线射频标签(扬州)有限公司 | 一种覆晶芯片与软性基板封装的结构及方法 |
KR102041108B1 (ko) * | 2018-03-26 | 2019-11-07 | 한국생산기술연구원 | 휨 개선 칩 적층 구조 패키지 및 이의 제조방법 |
US11165010B2 (en) | 2019-02-11 | 2021-11-02 | International Business Machines Corporation | Cold-welded flip chip interconnect structure |
CN109904139B (zh) * | 2019-03-08 | 2020-12-25 | 中国科学院微电子研究所 | 带有柔性转接板的大尺寸芯片***封装结构及其制作方法 |
CN112234122B (zh) * | 2020-10-15 | 2022-05-27 | 青岛融合装备科技有限公司 | 一种硅基太阳能电池的制造设备 |
TWI806490B (zh) * | 2022-03-14 | 2023-06-21 | 巨擘科技股份有限公司 | 封裝基板結構 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04154136A (ja) * | 1990-10-18 | 1992-05-27 | Fujitsu Ltd | ベアチップの実装方法 |
JPH09148374A (ja) * | 1995-11-24 | 1997-06-06 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH11340267A (ja) * | 1998-05-28 | 1999-12-10 | Sony Corp | 半導体チップとその製造方法および半導体装置 |
JP2000208907A (ja) * | 1999-01-18 | 2000-07-28 | Matsushita Electric Ind Co Ltd | 電子部品の実装方法 |
JP2003037135A (ja) * | 2001-07-24 | 2003-02-07 | Hitachi Cable Ltd | 配線基板及びその製造方法 |
JP2006303239A (ja) * | 2005-04-21 | 2006-11-02 | Matsushita Electric Works Ltd | 半導体装置及びその製造方法 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6163462A (en) * | 1997-12-08 | 2000-12-19 | Analog Devices, Inc. | Stress relief substrate for solder ball grid array mounted circuits and method of packaging |
US6816385B1 (en) * | 2000-11-16 | 2004-11-09 | International Business Machines Corporation | Compliant laminate connector |
JP2004281818A (ja) * | 2003-03-17 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、キャリア基板の製造方法、半導体装置の製造方法および電子デバイスの製造方法 |
JP4096774B2 (ja) * | 2003-03-24 | 2008-06-04 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法 |
TWM253159U (en) * | 2003-12-26 | 2004-12-11 | Inventec Appliances Corp | Internally installed spare card structure |
TWI253159B (en) * | 2004-12-23 | 2006-04-11 | Phoenix Prec Technology Corp | Combined soft and rigid sheet of flip chip substrate |
JP2006202991A (ja) * | 2005-01-20 | 2006-08-03 | Sony Corp | 回路基板及びその製造方法、並びに半導体パッケージ及びその製造方法 |
JP5116268B2 (ja) * | 2005-08-31 | 2013-01-09 | キヤノン株式会社 | 積層型半導体装置およびその製造方法 |
US20080185705A1 (en) * | 2005-12-23 | 2008-08-07 | Tessera, Inc. | Microelectronic packages and methods therefor |
KR101131138B1 (ko) * | 2006-01-04 | 2012-04-03 | 삼성전자주식회사 | 다양한 크기의 볼 패드를 갖는 배선기판과, 그를 갖는반도체 패키지 및 그를 이용한 적층 패키지 |
KR100831562B1 (ko) * | 2006-03-23 | 2008-05-21 | 주식회사 엘지화학 | 유연성 기판 반송용 점착제 조성물 |
DE102006044525B3 (de) * | 2006-09-21 | 2008-01-31 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zur Herstellung von gemeinsam bereitstellbaren flexiblen integrierten Schaltkreisen |
US20080150101A1 (en) * | 2006-12-20 | 2008-06-26 | Tessera, Inc. | Microelectronic packages having improved input/output connections and methods therefor |
TWI360205B (en) * | 2007-06-20 | 2012-03-11 | Princo Corp | Multi-layer substrate and manufacture method there |
JP2009049499A (ja) * | 2007-08-14 | 2009-03-05 | Fujifilm Corp | 半導体チップの実装方法及び半導体装置 |
US20090057866A1 (en) * | 2007-08-27 | 2009-03-05 | Chow Linda L W | Microelectronic Package Having Second Level Interconnects Including Stud Bumps and Method of Forming Same |
US8207473B2 (en) * | 2008-06-24 | 2012-06-26 | Imec | Method for manufacturing a stretchable electronic device |
US8604614B2 (en) * | 2010-03-26 | 2013-12-10 | Samsung Electronics Co., Ltd. | Semiconductor packages having warpage compensation |
JP2011243683A (ja) * | 2010-05-17 | 2011-12-01 | Fujitsu Ltd | 電子部品の実装方法、電子部品の製造方法および電子部品、電子部品の製造装置 |
US8580607B2 (en) * | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
KR101712043B1 (ko) * | 2010-10-14 | 2017-03-03 | 삼성전자주식회사 | 적층 반도체 패키지, 상기 적층 반도체 패키지를 포함하는 반도체 장치 및 상기 적층 반도체 패키지의 제조 방법 |
KR20120054371A (ko) * | 2010-11-19 | 2012-05-30 | 에스케이하이닉스 주식회사 | 원통형 패키지, 이를 이용한 전자장치 및 그 제조방법 |
KR102050476B1 (ko) * | 2012-09-28 | 2019-11-29 | 삼성전자주식회사 | 반도체 패키지 장치 |
US9385098B2 (en) * | 2012-11-21 | 2016-07-05 | Nvidia Corporation | Variable-size solder bump structures for integrated circuit packaging |
-
2012
- 2012-12-17 TW TW101147927A patent/TWI546911B/zh active
-
2013
- 2013-01-24 CN CN201310025212.0A patent/CN103871990A/zh active Pending
- 2013-11-13 US US14/079,377 patent/US20140167255A1/en not_active Abandoned
- 2013-11-13 EP EP13192760.0A patent/EP2750186A3/en not_active Withdrawn
- 2013-12-04 KR KR1020130149619A patent/KR20140078541A/ko not_active Application Discontinuation
- 2013-12-10 JP JP2013254874A patent/JP2014120773A/ja active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04154136A (ja) * | 1990-10-18 | 1992-05-27 | Fujitsu Ltd | ベアチップの実装方法 |
JPH09148374A (ja) * | 1995-11-24 | 1997-06-06 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH11340267A (ja) * | 1998-05-28 | 1999-12-10 | Sony Corp | 半導体チップとその製造方法および半導体装置 |
JP2000208907A (ja) * | 1999-01-18 | 2000-07-28 | Matsushita Electric Ind Co Ltd | 電子部品の実装方法 |
JP2003037135A (ja) * | 2001-07-24 | 2003-02-07 | Hitachi Cable Ltd | 配線基板及びその製造方法 |
JP2006303239A (ja) * | 2005-04-21 | 2006-11-02 | Matsushita Electric Works Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20140167255A1 (en) | 2014-06-19 |
KR20140078541A (ko) | 2014-06-25 |
EP2750186A2 (en) | 2014-07-02 |
EP2750186A3 (en) | 2018-01-24 |
CN103871990A (zh) | 2014-06-18 |
TWI546911B (zh) | 2016-08-21 |
TW201426924A (zh) | 2014-07-01 |
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