JP2012527113A - 超接合半導体装置 - Google Patents
超接合半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 12
- 239000002344 surface layer Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 230000001052 transient effect Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 230000007935 neutral effect Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000036961 partial effect Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
【解決手段】ストライプ状の平行表面パターンを有する超接合構造を備え、超接合ストライプとMOSセル6ストライプが平行であって、MOSセル6ストライプが上部に配置されないpカラムY2と、MOSセル6ストライプが上部に配置されたpカラムY1とを端部で連結する。
【選択図】図1
Description
さらに、また、前記導電接続が、前記超接合構造の前記第二導電型層の端部で連結される前記高濃度第二導電型ベース領域によりなされている構造とすることがより好ましい。
2 エピタキシャル成長層
4 n型バッファ層
5 pnカラム
6 MOSセル
7 ゲート絶縁膜
8 ゲート電極
9 pベース層
9−1 高濃度p+層
10 層間絶縁膜
Y1、Y2 pカラム
Lg ゲート幅
100 従来のSJ−MOSFET
101 本発明のSJ−MOSFET
Claims (4)
- 第一導電型の半導体基板の主面上に、該主面に垂直方向に形成される複数の薄層状の第一導電型層および第二導電型層が、前記主面に平行な面方向では、交互に繰り返し並列配置される超接合構造と、該超接合構造の前記第二導電型層の表層に長手方向に沿ってオーバーラップするように形成される高濃度第二導電型ベース領域と、該高濃度第二導電型ベース領域の表層に長手方向に沿って選択的に形成される高濃度第一導電型ソース領域と、前記薄板状の第一導電型層と前記高濃度第一導電型ソース領域とに挟まれる高濃度第二導電型ベース領域の表面上に絶縁膜を介して長手方向に沿って形成されるゲート電極とを備える超接合半導体装置において、
前記ゲート電極の下層に絶縁膜を介して長手方向に沿って前記超接合構造の前記第二導電型層を備えるとともに、前記超接合構造の前記第二導電型層は活性領域内の端部で全てが導電接続されていることを特徴とする超接合半導体装置。 - 前記導電接続が、端部で相互に連結される前記超接合構造の前記第二導電型層によりなされる構造を備えることを特徴とする請求項1に記載の超接合半導体装置。
- 前記導電接続が、前記超接合構造の前記第二導電型層の端部で連結される前記高濃度第二導電型ベース領域によりなされる構造を備えることを特徴とする請求項1または2に記載の超接合半導体装置。
- 前記導電接続が、前記超接合構造の前記第二導電型層の端部表面を連結するように形成される導電層または金属膜によりなされることを特徴とする請求項1に記載の超接合半導体装置。
Priority Applications (1)
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---|---|---|---|
JP2012510478A JP5423882B2 (ja) | 2009-07-15 | 2010-07-13 | 超接合半導体装置 |
Applications Claiming Priority (4)
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---|---|---|---|
JP2009166784 | 2009-07-15 | ||
JP2009166784 | 2009-07-15 | ||
JP2012510478A JP5423882B2 (ja) | 2009-07-15 | 2010-07-13 | 超接合半導体装置 |
PCT/JP2010/004549 WO2011007560A1 (en) | 2009-07-15 | 2010-07-13 | Super-junction semiconductor device |
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JP2012527113A true JP2012527113A (ja) | 2012-11-01 |
JP5423882B2 JP5423882B2 (ja) | 2014-02-19 |
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JP2012510478A Active JP5423882B2 (ja) | 2009-07-15 | 2010-07-13 | 超接合半導体装置 |
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US (1) | US9312330B2 (ja) |
JP (1) | JP5423882B2 (ja) |
CN (1) | CN102439727B (ja) |
WO (1) | WO2011007560A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6254301B1 (ja) * | 2016-09-02 | 2017-12-27 | 新電元工業株式会社 | Mosfet及び電力変換回路 |
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CN103578999A (zh) * | 2012-08-01 | 2014-02-12 | 上海华虹Nec电子有限公司 | 一种超级结的制备工艺方法 |
JP2014038963A (ja) * | 2012-08-17 | 2014-02-27 | Rohm Co Ltd | 半導体装置 |
TW201430957A (zh) * | 2013-01-25 | 2014-08-01 | Anpec Electronics Corp | 半導體功率元件的製作方法 |
JP2015018951A (ja) * | 2013-07-11 | 2015-01-29 | 株式会社東芝 | 半導体装置 |
CN105679830A (zh) * | 2016-01-29 | 2016-06-15 | 上海华虹宏力半导体制造有限公司 | 超级结器件 |
CN107591446B (zh) * | 2016-07-07 | 2021-01-12 | 深圳尚阳通科技有限公司 | 超结器件及其制造方法 |
CN107591445B (zh) * | 2016-07-07 | 2021-11-02 | 深圳尚阳通科技有限公司 | 超结器件及其制造方法 |
CN107591448A (zh) * | 2016-07-07 | 2018-01-16 | 深圳尚阳通科技有限公司 | 超结器件及其制造方法 |
US9899508B1 (en) | 2016-10-10 | 2018-02-20 | Stmicroelectronics S.R.L. | Super junction semiconductor device for RF applications, linear region operation and related manufacturing process |
JP2019071384A (ja) | 2017-10-11 | 2019-05-09 | 株式会社東芝 | 半導体装置 |
IT201800006323A1 (it) | 2018-06-14 | 2019-12-14 | Dispositivo a semiconduttore del tipo a bilanciamento di carica, in particolare per applicazioni rf ad elevata efficienza, e relativo procedimento di fabbricazione | |
DE112019003790T5 (de) * | 2018-11-29 | 2021-04-22 | Fuji Electric Co., Ltd. | Superjunction-siliziumkarbid-halbleitervorrichtung und verfahren zum herstellen einer superjunction-siliziumkarbid-halbleitervorrichtung |
CN109616517A (zh) * | 2018-12-12 | 2019-04-12 | 中国科学院微电子研究所 | 基区电阻控制晶闸管、发射极开关晶闸管及制备方法 |
CN116544269B (zh) * | 2023-07-06 | 2023-09-12 | 无锡美偌科微电子有限公司 | 提高终端耐压能力的电荷平衡功率半导体器件 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002083962A (ja) * | 1999-10-21 | 2002-03-22 | Fuji Electric Co Ltd | 半導体素子およびその製造方法 |
JP2004006598A (ja) * | 2002-04-26 | 2004-01-08 | Toshiba Corp | 絶縁ゲート型半導体装置 |
JP2006156989A (ja) * | 2004-11-05 | 2006-06-15 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2007243092A (ja) * | 2006-03-13 | 2007-09-20 | Toyota Motor Corp | 半導体装置とその製造方法 |
JP2007335844A (ja) * | 2006-05-16 | 2007-12-27 | Toshiba Corp | 半導体装置 |
JP2008258327A (ja) * | 2007-04-03 | 2008-10-23 | Toshiba Corp | 電力用半導体素子 |
JP2011018877A (ja) * | 2009-06-09 | 2011-01-27 | Toshiba Corp | 電力用半導体素子 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6936892B2 (en) * | 1998-07-24 | 2005-08-30 | Fuji Electric Co., Ltd. | Semiconductor device with alternating conductivity type layer and method of manufacturing the same |
JP3988262B2 (ja) * | 1998-07-24 | 2007-10-10 | 富士電機デバイステクノロジー株式会社 | 縦型超接合半導体素子およびその製造方法 |
US6677626B1 (en) * | 1998-11-11 | 2004-01-13 | Fuji Electric Co., Ltd. | Semiconductor device with alternating conductivity type layer and method of manufacturing the same |
US6291856B1 (en) * | 1998-11-12 | 2001-09-18 | Fuji Electric Co., Ltd. | Semiconductor device with alternating conductivity type layer and method of manufacturing the same |
JP4447065B2 (ja) * | 1999-01-11 | 2010-04-07 | 富士電機システムズ株式会社 | 超接合半導体素子の製造方法 |
US6204097B1 (en) * | 1999-03-01 | 2001-03-20 | Semiconductor Components Industries, Llc | Semiconductor device and method of manufacture |
JP2001119022A (ja) * | 1999-10-20 | 2001-04-27 | Fuji Electric Co Ltd | 半導体装置及びその製造方法 |
US6475864B1 (en) * | 1999-10-21 | 2002-11-05 | Fuji Electric Co., Ltd. | Method of manufacturing a super-junction semiconductor device with an conductivity type layer |
JP4843843B2 (ja) * | 2000-10-20 | 2011-12-21 | 富士電機株式会社 | 超接合半導体素子 |
DE10205345B9 (de) * | 2001-02-09 | 2007-12-20 | Fuji Electric Co., Ltd., Kawasaki | Halbleiterbauelement |
US6777746B2 (en) * | 2002-03-27 | 2004-08-17 | Kabushiki Kaisha Toshiba | Field effect transistor and application device thereof |
DE10321222A1 (de) * | 2003-05-12 | 2004-12-23 | Infineon Technologies Ag | Halbleiterbauelement |
JP4940535B2 (ja) * | 2004-01-08 | 2012-05-30 | 株式会社豊田中央研究所 | 半導体装置 |
JP2006278826A (ja) * | 2005-03-30 | 2006-10-12 | Toshiba Corp | 半導体素子及びその製造方法 |
JP4735067B2 (ja) | 2005-06-14 | 2011-07-27 | トヨタ自動車株式会社 | 絶縁ゲート型半導体装置 |
JP2007012858A (ja) * | 2005-06-30 | 2007-01-18 | Toshiba Corp | 半導体素子及びその製造方法 |
JP4996848B2 (ja) * | 2005-11-30 | 2012-08-08 | 株式会社東芝 | 半導体装置 |
US7737469B2 (en) * | 2006-05-16 | 2010-06-15 | Kabushiki Kaisha Toshiba | Semiconductor device having superjunction structure formed of p-type and n-type pillar regions |
JP2008010896A (ja) | 2007-09-28 | 2008-01-17 | Seiko Epson Corp | 半導体集積回路の配線構造及び配線形成方法 |
-
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- 2010-07-13 JP JP2012510478A patent/JP5423882B2/ja active Active
- 2010-07-13 US US13/319,756 patent/US9312330B2/en active Active
- 2010-07-13 WO PCT/JP2010/004549 patent/WO2011007560A1/en active Application Filing
- 2010-07-13 CN CN201080021229.3A patent/CN102439727B/zh active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002083962A (ja) * | 1999-10-21 | 2002-03-22 | Fuji Electric Co Ltd | 半導体素子およびその製造方法 |
JP2004006598A (ja) * | 2002-04-26 | 2004-01-08 | Toshiba Corp | 絶縁ゲート型半導体装置 |
JP2006156989A (ja) * | 2004-11-05 | 2006-06-15 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2007243092A (ja) * | 2006-03-13 | 2007-09-20 | Toyota Motor Corp | 半導体装置とその製造方法 |
JP2007335844A (ja) * | 2006-05-16 | 2007-12-27 | Toshiba Corp | 半導体装置 |
JP2008258327A (ja) * | 2007-04-03 | 2008-10-23 | Toshiba Corp | 電力用半導体素子 |
JP2011018877A (ja) * | 2009-06-09 | 2011-01-27 | Toshiba Corp | 電力用半導体素子 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6254301B1 (ja) * | 2016-09-02 | 2017-12-27 | 新電元工業株式会社 | Mosfet及び電力変換回路 |
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JP5423882B2 (ja) | 2014-02-19 |
WO2011007560A1 (en) | 2011-01-20 |
CN102439727A (zh) | 2012-05-02 |
CN102439727B (zh) | 2015-05-20 |
US20120086076A1 (en) | 2012-04-12 |
US9312330B2 (en) | 2016-04-12 |
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