JP2007335844A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 166
- 239000012535 impurity Substances 0.000 claims description 88
- 230000007423 decrease Effects 0.000 claims description 20
- 230000000737 periodic effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 27
- 230000008569 process Effects 0.000 abstract description 27
- 230000006866 deterioration Effects 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 47
- 238000010586 diagram Methods 0.000 description 19
- 230000005684 electric field Effects 0.000 description 18
- 230000008859 change Effects 0.000 description 14
- 238000005468 ion implantation Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000001459 lithography Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000012010 growth Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
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Abstract
【解決手段】半導体装置は、素子領域50と終端部60とに分けられ、素子領域50の素子中央領域51と終端部60との間には、高抵抗半導体層12に隣接する第1の半導体ピラー領域3及び第2の半導体ピラー領域4の深さが、終端部60に向かうにしたがって段階的に浅くなる境界領域52が設けられたスーパージャンクション構造部があり、境界領域52は、制御電極8よりも終端部60側に位置している。
【選択図】図1
Description
図1は本発明の第1の実施形態に係る半導体装置の要部断面構造を例示する模式図である。
図2は、本実施形態に係る半導体装置においてピラー領域の平面パターンの一例を示す模式図である。
なお、図1は、図2におけるA−A断面を表す。
図9(a)は、本発明の第2の実施形態に係る半導体装置の要部断面構造を例示する模式図であり、図9(b)は、図9(a)に表されるピラー領域の不純物濃度の横方向(素子中央領域から終端部に向かう方向)の変化を表す模式図である。図9(b)における縦軸は、ピラー領域の不純物濃度を表す。
図12は、本発明の第3の実施形態に係る半導体装置における、ピラー領域形成用マスクの開口パターンを例示する模式図である。
図13は、図12におけるC−C断面部分に注入された不純物を表す模式図である。
図14は、図12におけるD−D断面部分に注入された不純物を表す模式図である。
図15は、図12におけるE−E断面部分に注入された不純物を表す模式図である。
図16(a)は、本発明の第4の実施形態に係る半導体装置の要部断面構造を例示する模式図であり、図16(b)は、図16(a)に表されるピラー領域の深さ方向(縦方向)の不純物濃度の変化を表す模式図である。図16(b)において、実線はp型ピラー領域4の不純物濃度プロファイルを表し、点線はn型ピラー領域3の不純物濃度プロファイルを表す。
図17は、本発明の第5の実施形態に係る半導体装置の要部断面構造を例示する模式図である。
図20は、本発明の第6の実施形態に係る半導体装置の要部断面構造を例示する模式図である。
図21は、本発明の第7の実施形態に係る半導体装置の要部断面構造を例示する模式図である。
図22は、本実施形態に係る半導体装置における、ピラー領域形成用マスクの開口パターンと、埋め込みガードリング層22との位置関係を例示する模式図である。
図24は、本発明の第8の実施形態に係る半導体装置の要部断面構造を例示する模式図である。
このような構造とすることで、図10に示したような濃度遷移領域を設けなくとも高耐圧を実現することができる。これにより、素子有効面積が大きくなって、チップオン抵抗を下げることが可能となる。また、境界領域の耐圧を確実にセル部よりも高くするために、図に示す構造に濃度遷移領域を加えても実施可能である。
図27は本発明の第9の実施形態に係る半導体装置の要部断面構造を例示する模式図である。
図28は、本実施形態に係る半導体装置においてピラー領域の平面パターンの一例を示す模式図である。
なお、図27は、図28におけるC−C断面を表す。
Claims (5)
- 第1導電型の半導体層と、
前記半導体層の主面上に設けられた第1導電型の第1の半導体ピラー領域と、
前記半導体層の前記主面に対して略平行な方向に前記第1の半導体ピラー領域と共に周期的配列構造を形成するように、前記第1の半導体ピラー領域に隣接して前記半導体層の前記主面上に設けられた第2導電型の第2の半導体ピラー領域と、
前記半導体層の前記主面の反対側に設けられた第1の主電極と、
前記第1の半導体ピラー領域及び前記第2の半導体ピラー領域の上に選択的に設けられた第2導電型の第1の半導体領域と、
前記第1の半導体領域の表面に選択的に設けられた第1導電型の第2の半導体領域と、
前記第1の半導体領域及び前記第2の半導体領域に接して設けられた第2の主電極と、
前記第1の半導体領域、前記第2の半導体領域および前記第1の半導体ピラー領域の上に絶縁膜を介して設けられた制御電極と、
前記第1の半導体ピラー領域及び前記第2の半導体ピラー領域を囲む終端部における前記半導体層上に設けられ、前記第1の半導体ピラー領域よりも不純物濃度が低い高抵抗半導体層と、
を備え、
素子中央領域と前記終端部との間に、前記高抵抗半導体層に隣接する前記第1の半導体ピラー領域及び前記第2の半導体ピラー領域の深さが、前記終端部に向かうにしたがって段階的に浅くなる境界領域が設けられたことを特徴とする半導体装置。 - 前記境界領域における前記第1の半導体ピラー領域及び前記第2の半導体ピラー領域の不純物濃度が、前記素子中央領域における前記第1の半導体ピラー領域及び前記第2の半導体ピラー領域の不純物濃度よりも低いことを特徴とする請求項1記載の半導体装置。
- 前記素子中央領域から前記境界領域にかけて前記第1の半導体ピラー領域及び前記第2の半導体ピラー領域の不純物濃度が徐々に低下していることを特徴とする請求項2記載の半導体装置。
- 前記境界領域が、前記第1の主電極から前記第2の主電極に向かう方向に対して略垂直ないずれか一方向において、階段状に配置されていることを特徴とする請求項1〜3のいずれか1つに記載の半導体装置。
- 前記半導体層と、前記第1の半導体ピラー領域及び前記第2の半導体ピラー領域と、の間に第1導電型半導体のバッファー層を設けたことを特徴とする請求項1〜4のいずれか1つに記載の半導体装置。
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JP2007100460A JP5342752B2 (ja) | 2006-05-16 | 2007-04-06 | 半導体装置 |
US11/748,869 US7737469B2 (en) | 2006-05-16 | 2007-05-15 | Semiconductor device having superjunction structure formed of p-type and n-type pillar regions |
US12/764,763 US8013360B2 (en) | 2006-05-16 | 2010-04-21 | Semiconductor device having a junction of P type pillar region and N type pillar region |
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JP2007100460A JP5342752B2 (ja) | 2006-05-16 | 2007-04-06 | 半導体装置 |
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Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011007560A1 (en) * | 2009-07-15 | 2011-01-20 | Fuji Electric Systems Co., Ltd. | Super-junction semiconductor device |
JP2011181805A (ja) * | 2010-03-03 | 2011-09-15 | Toshiba Corp | 半導体装置 |
US8097914B2 (en) | 2008-08-29 | 2012-01-17 | Sony Corporation | Semiconductor device and manufacturing method of the same |
JP2012060017A (ja) * | 2010-09-10 | 2012-03-22 | Toshiba Corp | 電力用半導体装置及びその製造方法 |
JP2014138077A (ja) * | 2013-01-16 | 2014-07-28 | Fuji Electric Co Ltd | 半導体素子 |
US8872261B2 (en) | 2011-09-21 | 2014-10-28 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method of the same |
JP2016127245A (ja) * | 2015-01-08 | 2016-07-11 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
JP2016197633A (ja) * | 2015-04-02 | 2016-11-24 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP2017126600A (ja) * | 2016-01-12 | 2017-07-20 | 富士電機株式会社 | 半導体装置 |
JP2020202404A (ja) * | 2020-09-18 | 2020-12-17 | 富士電機株式会社 | 半導体装置およびその製造方法 |
CN115497934A (zh) * | 2022-10-09 | 2022-12-20 | 上海功成半导体科技有限公司 | 一种超结器件终端保护的版图结构 |
JP7443702B2 (ja) | 2019-09-10 | 2024-03-06 | 富士電機株式会社 | 半導体装置 |
Citations (11)
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