JP2011129904A - 信号雑音を低減する方法および装置 - Google Patents
信号雑音を低減する方法および装置 Download PDFInfo
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- JP2011129904A JP2011129904A JP2010271350A JP2010271350A JP2011129904A JP 2011129904 A JP2011129904 A JP 2011129904A JP 2010271350 A JP2010271350 A JP 2010271350A JP 2010271350 A JP2010271350 A JP 2010271350A JP 2011129904 A JP2011129904 A JP 2011129904A
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- vias
- circuit board
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- electrical signal
- conductive
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- 238000000034 method Methods 0.000 title claims abstract description 8
- 230000002093 peripheral effect Effects 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 10
- IYZWUWBAFUBNCH-UHFFFAOYSA-N 2,6-dichlorobiphenyl Chemical compound ClC1=CC=CC(Cl)=C1C1=CC=CC=C1 IYZWUWBAFUBNCH-UHFFFAOYSA-N 0.000 description 6
- 230000008901 benefit Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09618—Via fence, i.e. one-dimensional array of vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
【解決手段】少なくとも2つの離間した導電性平面を有するプリント回路板。複数のビアは、2つの離間した導電性平面間に延在し、ビアは、2つの導電性平面のうちの選択された一方の平面に交互パターンで電気接続される。差動電気信号は、差動電気信号が導電性平面に接続されると、ビアが差動電気信号によって交互に電圧印加されるように導電性平面に接続可能である。
【選択図】図1
Description
12 誘電性基板
16 第1の導電性平面
18 第2の導電性平面
30、30a,30b ビア
40 回路要素
50 コンプライアントピン
52 起動可能乗員拘束システム
54 ハウジング
60 中央ECU
62 コネクタ
64 他の中央衝突状態センサ
66 他の遠隔衝突状態センサ
70 起動可能拘束部
Claims (7)
- 少なくとも2つの離間した導電性平面を含むプリント回路板と、
前記2つの離間した導電性平面間に延在する複数のビアであって、前記2つの導電性平面のうちの選択された一方の平面に交互パターンで電気接続される、複数のビアと、
差動電気信号であって、差動電気信号が前記導電性平面に接続されると、前記ビアが前記差動電気信号によって交互に電圧印加されるように前記導電性平面に接続可能である、差動電気信号とを備える装置。 - 請求項1に記載の装置において、前記複数のビアは、前記プリント回路板の外周縁部の少なくとも一部分の近くに配置される装置。
- 請求項2に記載の装置において、前記差動電気信号を前記プリント回路板に提供するコネクタをさらに含み、前記ビアは、前記コネクタまで、前記プリント回路板の全周縁部にわたって延在する装置。
- プリント回路板であって、
非導電性基板および少なくとも2つの離間した導体と、
前記非導電性基板を貫通して延在し、かつ、前記2つの導体の選択されたうちの一方の導体に交互パターンで電気接続される複数のビアと、
差動電気信号であって、前記ビアが前記差動電気信号によって交互に電圧印加されるように前記導体に接続可能である差動電気信号とを備えるプリント回路板。 - 請求項4に記載のプリント回路板において、前記2つの導体は、前記非導電性基板の両面に形成された導電性平面であるプリント回路板。
- 電気システム内の電気信号雑音を低減する方法であって、
プリント回路板を設けるステップと、
前記プリント回路板上に2つの離間した導電性平面を作製するステップと、
前記2つの離間した導電性平面間に複数のビアを延在させるステップと、
前記2つの導電性平面のうちの選択された一方の平面に前記ビアを交互パターンで電気接続するステップと、
差動電気信号を前記導電性平面に接続するステップであって、それにより、前記ビアが前記差動電気信号に交互に接続される、接続するステップとを含む方法。 - 請求項6に記載の方法において、前記複数のビアを延在させるステップは、前記プリント回路板の外周縁部の少なくとも一部分の近くに前記ビアを配置することを含む方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/643,129 | 2009-12-21 | ||
US12/643,129 US8664537B2 (en) | 2009-12-21 | 2009-12-21 | Method and apparatus for reducing signal noise |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011129904A true JP2011129904A (ja) | 2011-06-30 |
JP5264870B2 JP5264870B2 (ja) | 2013-08-14 |
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JP2010271350A Active JP5264870B2 (ja) | 2009-12-21 | 2010-12-06 | 信号雑音を低減する方法および装置並びにプリント回路板 |
Country Status (2)
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US (1) | US8664537B2 (ja) |
JP (1) | JP5264870B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102348323A (zh) * | 2010-08-02 | 2012-02-08 | 鸿富锦精密工业(深圳)有限公司 | 电路板 |
US20130319731A1 (en) * | 2012-05-30 | 2013-12-05 | Sts Semiconductor & Telecommunications Co., Ltd. | Printed circuit board of semiconductor package for decreasing noise by electromagnetic interference |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0864987A (ja) * | 1994-08-24 | 1996-03-08 | Matsushita Electric Ind Co Ltd | プリント基板のシールド装置 |
JPH11251694A (ja) * | 1998-03-05 | 1999-09-17 | Fujitsu Denso Ltd | プリント配線板およびプリント配線板用収納箱の電磁遮蔽構造 |
JP2009044151A (ja) * | 2007-08-07 | 2009-02-26 | Samsung Electro Mech Co Ltd | 電磁気バンドギャップ構造物及び印刷回路基板 |
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US20030047348A1 (en) | 2001-09-10 | 2003-03-13 | Rebecca Jessep | Grid array mounting arrangements |
US6573590B1 (en) * | 2002-02-11 | 2003-06-03 | Sun Microsystems, Inc. | Integrated circuit package with EMI containment features |
US6815812B2 (en) * | 2002-05-08 | 2004-11-09 | Lsi Logic Corporation | Direct alignment of contacts |
US7030712B2 (en) | 2004-03-01 | 2006-04-18 | Belair Networks Inc. | Radio frequency (RF) circuit board topology |
CN100502614C (zh) | 2004-10-09 | 2009-06-17 | 鸿富锦精密工业(深圳)有限公司 | 适用于高速信号的印刷电路板结构 |
JP4551730B2 (ja) * | 2004-10-15 | 2010-09-29 | イビデン株式会社 | 多層コア基板及びその製造方法 |
US7355836B2 (en) * | 2005-06-07 | 2008-04-08 | Intel Corporation | Array capacitor for decoupling multiple voltage rails |
US7851709B2 (en) * | 2006-03-22 | 2010-12-14 | Advanced Semiconductor Engineering, Inc. | Multi-layer circuit board having ground shielding walls |
KR100881182B1 (ko) * | 2006-11-21 | 2009-02-05 | 삼성전자주식회사 | 웨이퍼 사이에 형성된 디커플링 커패시터, 그 디커플링커패시터를 포함하는 웨이퍼 스택 패키지, 및 그 패키지제조 방법 |
US7742276B2 (en) * | 2007-03-30 | 2010-06-22 | Industrial Technology Research Institute | Wiring structure of laminated capacitors |
US20090002952A1 (en) | 2007-06-28 | 2009-01-01 | Ralph Mesmer | Interference mitigation |
KR100779431B1 (ko) * | 2007-07-19 | 2007-11-26 | 브로콜리 주식회사 | 전자파 차폐기능을 갖는 평면 균일 전송선로 |
US7977582B2 (en) * | 2008-01-28 | 2011-07-12 | International Business Machines Corporation | Flexible multilayer printed circuit assembly with reduced EMI emissions |
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2009
- 2009-12-21 US US12/643,129 patent/US8664537B2/en active Active
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- 2010-12-06 JP JP2010271350A patent/JP5264870B2/ja active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0864987A (ja) * | 1994-08-24 | 1996-03-08 | Matsushita Electric Ind Co Ltd | プリント基板のシールド装置 |
JPH11251694A (ja) * | 1998-03-05 | 1999-09-17 | Fujitsu Denso Ltd | プリント配線板およびプリント配線板用収納箱の電磁遮蔽構造 |
JP2009044151A (ja) * | 2007-08-07 | 2009-02-26 | Samsung Electro Mech Co Ltd | 電磁気バンドギャップ構造物及び印刷回路基板 |
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US8664537B2 (en) | 2014-03-04 |
JP5264870B2 (ja) | 2013-08-14 |
US20110147070A1 (en) | 2011-06-23 |
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