CN100502614C - 适用于高速信号的印刷电路板结构 - Google Patents
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- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
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- H—ELECTRICITY
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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Abstract
一种适用于高速信号的印刷电路板结构,包括若干布线层以及若干参考平面层,所述印刷电路板上开设一贯穿的供信号线穿过的开孔,一缝合贯孔布设于其中一参考平面层,所述缝合贯孔与所述参考平面层完全电连接。从而使信号线中的信号电流与其回返电流构成一完整的电流回路,避免印刷电路板上杂讯和串扰的发生。
Description
【技术领域】
本发明是涉及一种印刷电路板结构,特别是涉及一种适用于高速信号的保持信号完整的印刷电路板结构。
【背景技术】
高速线路通常都是用多层板来布线,为了要尽可能将布线通道有效率的利用,设计者通常会在一个布线层走横向的线,在另一个布线层走纵向的线。信号必然要变更布线层以到达接收端,另外,由于目前印刷电路板上的信号密度逐渐提高,就需要更多的的信号传输层,因此通过层间互连也就是导孔(via)实现传输也是不可避免的。
高速电路中要构成完整的电流回路,必定有返回电流存在于电路中,高速电路设计中,地平面或电源平面都可以作为返回电流的参考平面。当高速信号经过不同的布线层时,作为构成电路完整回路的返回电流也会同时变更参考平面。如图1所示,显示一基本的四层板,1、4分别为第一布线层及第二布线层,2、3分别为电源层及接地层,线路布线6通过一贯穿孔8进行布线,从而其布线层从第一布线层1变换至第二布线层4,此时,对于高频电路来说,返回电流11的路径为经过电源层2、接地层3之间电容(Interplane Capacitance)的位移电流(Displacement Current),从而返回电流11从下面的接地层3走到上层的电源层2,而这些位移电流11就会造成电源层2、接地层3两个参考平面间分布面积广大的杂讯(Noise),当有两个以上的线路布线同时进行布线时,就会形成严重的串扰。
针对这一问题,目前,设计者通常在两参考平面层之间加上缝补电容,以提供有利的返回电流路径。如图2所示,为一个代表性的回返电流路径图,此时回返电流12沿着接地层3的下表面流过贯穿孔8,流到接地层3的上表面,再经过缝补电容沿着电源层2的下表面流到贯穿孔8的开孔处,最后到达第一布线层2的上表面,当回返电流经过该缝补电容之阻抗小于其中存在的位移电流路径的阻抗时,则回返电流主要经由缝补电容,从而避免大规模杂讯的发生。但是,一些回返电流变成共模电流(Common-Mode Current),在电源层2的上表面流动,造成直接的辐射,且当流经缝补电容的阻抗大于电源层2和接地层3间的位移电流路径的阻抗时,则此缝补电容也就没有多大作用了。并且,在电路板中加入缝补电容,增加了电路板制造的复杂度并大幅提高电路板的成本。
因此,实有必要提供一种适用于高速信号的且保持信号完整性,以有效消除信号杂讯及串扰的印刷电路板结构。
【发明内容】
本发明的目的在于提供一种适用于高速信号的,同时保持高速信号完整的印刷电路板结构。
为实现上述目的,本发明提供一种适用于高速信号的印刷电路板结构,其包括若干布线层以及若干参考平面层,所述若干参考平面层包括若干接地层及若干电源层,所述印刷电路板上开设一贯穿的供信号线穿过的开孔,使所述印刷电路板中的一信号电流通过所述开孔从一布线层流向另一布线层,一缝合贯孔布设于其中一参考平面层,所述缝合贯孔与所述参考平面层完全电连接,且沿所述缝合贯孔的方向所述若干布线层及若干参考平面层均被贯穿,使所述印刷电路板中的一信号回返电流通过所述缝合贯孔从一接地层流向一电源层,从而使得所述信号电流与信号回返电流构成一完整的电流回路。从而使信号线中的信号电流与其回返电流构成一完整的电流回路,避免印刷电路板上杂讯和串扰的发生。
本发明的优点在于,无须在印刷电路板上外加电容元件,即可以在信号线换布线层时,通过缝合贯孔保持信号电流的完整,从而避免印刷电路板中杂讯与串扰的发生。
【附图说明】
下面参照附图结合实施例对本发明作进一步的说明。
图1是现有印刷电路板结构及其中信号电流走向示意图。
图2是在现有印刷电路板结构中加入缝补电容后信号电流走向示意图。
图3是本发明印刷电路板结构及其中信号电流走向示意图。
图4是本发明另一印刷电路板结构及其中信号电流走向示意图。
【具体实施方式】
印刷电路板中,由于信号的流动产生电场,通常该电场能量用以下公式(1)计算:
E=2.6(AILf2) (1)
其中,A为印刷电路板中信号电流流经的回路面积,IL为信号电流,f为信号电流的频率。从公式(1)中得出,若要降低印刷电路板中的磁场,提升印刷电路板中的电磁干扰及电磁兼容能力,也既是减少印刷电路板中杂讯和串扰,必须减少印刷电路板中信号电流流经的回路面积A。
请参阅图3,为本发明的一具体实施例,一第一布线层1、一电源层2、一接地层3以及一第二布线层4共同构成一标准的四层印刷电路板,其中夹在该第一布线层1、该电源层2、该接地层3以及该第二布线层4之间的为印刷电路板的层间绝缘体14。该电源层2及该接地层3都可以作为信号电流的参考平面层。一信号线20布设在第一布线层1的上表面,并通过贯穿整个印刷电路板及绝缘体10的开孔8,从而变更其布线层至第二布线层4的下表面。图3中箭头代表流经该信号线20的信号电流30的流向,信号电流30顺着信号线20从第一布线层1的上表面流经开孔8至第二布线层4的下表面。一缝合贯孔40开设在该电源层2上,同时顺着该缝合贯孔40的方向该印刷电路板被贯穿。该缝合贯孔40的开设位置位于该信号线20穿过该电源层2的开孔8附近。该缝合贯孔40为一导电体,并与该电源层2完全电连接。则印刷电路板中的信号回返电流50从接地层3的下表面,流经该缝合贯孔40至该电源层2的上表面,从而使信号电流30与回返电流50构成一完整的电流回路,且该电流回路面积A较小,从而提升了印刷电路板的电磁干扰。
请参阅图4,为本发明的另一具体实施例,与图3不同的是,一缝合贯孔60开设在该接地层3上,同时顺着该缝合贯孔60的方向该印刷电路板被贯穿。该缝合贯孔60的开设位置位于该信号线20穿过该接地层3的开孔8附近。该缝合贯孔60为一导电体,并与该接地层2完全电连接。则印刷电路板中的信号回返电流50从接地层3的下表面,流经该缝合贯孔60至该电源层2的上表面,从而使信号电流30与回返电流50构成一完整的电流回路,且该电流回路面积A较小,从而提升了印刷电路板的电磁干扰。
本发明是以标准四层板为例,本发明同样适用于其他结构的印刷电路板,如六层板、八层板等,只须在作为参考平面层的电源层或接地层上布设一完全电连接与该电源层或接地层的缝合贯孔。
Claims (7)
1.一种适用于高速信号的印刷电路板结构,包括若干布线层以及若干参考平面层,所述若干参考平面层包括若干接地层及若干电源层,所述印刷电路板上开设一贯穿的供信号线穿过的开孔,使所述印刷电路板中的一信号电流通过所述开孔从一布线层流向另一布线层,其特征在于:一缝合贯孔布设于其中一参考平面层,所述缝合贯孔与所述参考平面层完全电连接,且沿所述缝合贯孔的方向所述若干布线层及若干参考平面层均被贯穿,使所述印刷电路板中的一信号回返电流通过所述缝合贯孔从一接地层流向一电源层,从而使得所述信号电流与信号回返电流构成一完整的电流回路。
2.如权利要求1所述的适用于高速信号的印刷电路板结构,其特征在于:所述缝合贯孔布设于所述参考平面层的开孔附近。
3.如权利要求2所述的适用于高速信号的印刷电路板结构,其特征在于:所述布设缝合贯孔的参考平面层为印刷电路板中的电源层。
4.如权利要求2所述的适用于高速信号的印刷电路板结构,其特征在于:所述布设缝合贯孔的参考平面层为印刷电路板中的接地层。
5.如权利要求3或4所述的适用于高速信号的印刷电路板结构,其特征在于:所述印刷电路板为四层板。
6.如权利要求3或4所述的适用于高速信号的印刷电路板结构,其特征在于:所述印刷电路板为六层板。
7.如权利要求3或4所述的适用于高速信号的印刷电路板结构,其特征在于:所述印刷电路板为八层板。
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CNB200410051838XA CN100502614C (zh) | 2004-10-09 | 2004-10-09 | 适用于高速信号的印刷电路板结构 |
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US6842344B1 (en) * | 2003-03-17 | 2005-01-11 | Unisys Corporation | Multi-layer printed circuit board and signal routing therein |
-
2004
- 2004-10-09 CN CNB200410051838XA patent/CN100502614C/zh not_active Expired - Fee Related
-
2005
- 2005-10-11 US US11/247,341 patent/US20060076160A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6777620B1 (en) * | 1999-12-02 | 2004-08-17 | Nec Corporation | Circuit board |
US20030024732A1 (en) * | 2000-05-31 | 2003-02-06 | Kabushiki Kaisha Toshiba | Printed circuit board and electronic equipment using the board |
US20040211590A1 (en) * | 2003-04-25 | 2004-10-28 | Matsushita Electric Industrial Co., Ltd. | Multilayer printed wiring board and integrated circuit using the same |
Also Published As
Publication number | Publication date |
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US20060076160A1 (en) | 2006-04-13 |
CN1758828A (zh) | 2006-04-12 |
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