JP2010205761A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01—ELECTRIC ELEMENTS
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H01L2924/1015—Shape
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- H01L2924/10158—Shape being other than a cuboid at the passive surface
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Abstract
【解決手段】第1主面に動作領域が設けられ、第2主面に金属層が設けられる半導体基板(半導体チップ)の、少なくとも動作領域と一部重畳する第2主面側の半導体基板に凹部を設ける。これにより周辺部において第1の厚みを有し、凹部において第1の厚みより薄化された第2の厚みを有する半導体チップとする。周辺部が第1の厚みを有するため、第2主面側に厚い金属層を形成しても、半導体チップの反りを防止できる。
【選択図】 図1
Description
2 n−型半導体層
4 チャネル層
7 トレンチ
10 半導体基板(半導体チップ)
11 ゲート絶縁膜
13 ゲート電極
13c 連結部
14 ボディ領域
15 ソース領域
16 層間絶縁膜
17、17a、17b ソース電極
18 ドレイン電極
19p、19pa、19pb ゲートパッド電極
20 凹部
22、22’ 高濃度不純物領域
23 窒化膜
24 UBM
25 保護膜
27 ソースバンプ電極
28 ドレインバンプ電極
29 ゲートバンプ電極
30 金属層
100、100a、100b MOSFET
200 スイッチング素子
E、Ea、Eb 動作領域
Sf1 第1主面
Sf2 第2主面
S、S1、S2 ソース端子(電極)
G、G1、G2 ゲート端子(電極)
D ドレイン端子(電極)
Claims (11)
- 第1主面と、第2主面を有する半導体基板と、
該半導体基板の前記第1主面側に設けられた動作領域と、
前記第2主面側の前記半導体基板に、該動作領域の少なくとも一部と重畳して設けられた凹部と、を具備することを特徴とする半導体装置。 - 前記凹部は、少なくとも1つの対向する側壁を有することを特徴とする請求項1に記載の半導体装置。
- 前記第2主面側を覆う金属層を具備することを特徴とする請求項2に記載の半導体装置。
- 前記凹部は、前記第2主面の前記動作領域全面と対向する領域に設けられることを特徴とする請求項2に記載の半導体装置。
- 前記凹部底部から前記第1主面表面までの厚みは、前記動作領域の特性上必要かつ十分な厚みが確保されることを特徴とする請求項2から請求項4に記載の半導体装置。
- 第1主面と第2主面を有する半導体ウエハを準備し、前記第1主面側にダイシングラインに沿って配列する複数の動作領域を形成し、それぞれの前記動作領域において、前記第1主面側に該動作領域と接続する電極を形成する工程と、
前記半導体ウエハの前記第2主面側を所望の厚みまで研削する工程と、
それぞれの前記動作領域において、該動作領域と少なくとも一部が重畳する領域の前記第2主面側の前記半導体ウエハに凹部を形成する工程と、
前記動作領域をダイシングラインに沿って個々に分割する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 前記凹部は、少なくとも1つの対向する側壁を有するように形成されることを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記第2主面側を研削した後、前記凹部をエッチングにより形成することを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記第2主面側を被覆する金属層を形成することを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記凹部は、前記第2主面の前記動作領域全面と対向する領域に形成することを特徴とする請求項7に記載の半導体装置。
- 前記凹部は、底部から前記第1主面表面までの厚みが、前記動作領域の特性上必要かつ十分となる深さに形成されることを特徴とする請求項8から請求項10に記載の半導体装置の製造方法。
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JP2009046354A JP2010205761A (ja) | 2009-02-27 | 2009-02-27 | 半導体装置およびその製造方法 |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013201413A (ja) * | 2012-02-21 | 2013-10-03 | Rohm Co Ltd | 半導体装置および半導体装置の製造方法 |
US9711434B2 (en) | 2015-09-17 | 2017-07-18 | Semiconductor Components Industries, Llc | Stacked semiconductor device structure and method |
JP6447946B1 (ja) * | 2018-01-19 | 2019-01-09 | パナソニックIpマネジメント株式会社 | 半導体装置および半導体モジュール |
US10854744B2 (en) | 2016-12-27 | 2020-12-01 | Panasonic Semiconductor Solutions Co., Ltd. | Semiconductor device |
JP2021015851A (ja) * | 2019-07-10 | 2021-02-12 | 株式会社東芝 | 半導体装置及び半導体装置の製造方法 |
US11342189B2 (en) | 2015-09-17 | 2022-05-24 | Semiconductor Components Industries, Llc | Semiconductor packages with die including cavities and related methods |
US11532618B2 (en) | 2021-03-30 | 2022-12-20 | Kabushiki Kaisha Toshiba | Semiconductor device |
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JP2002076326A (ja) * | 2000-09-04 | 2002-03-15 | Shindengen Electric Mfg Co Ltd | 半導体装置 |
JP2002368218A (ja) * | 2001-06-08 | 2002-12-20 | Sanyo Electric Co Ltd | 絶縁ゲート型半導体装置 |
JP2003243356A (ja) * | 2001-12-12 | 2003-08-29 | Denso Corp | 半導体装置の製造方法 |
JP2004281551A (ja) * | 2003-03-13 | 2004-10-07 | Toshiba Corp | 半導体基板及びその製造方法、半導体装置及びその製造方法、半導体パッケージ |
JP2007208074A (ja) * | 2006-02-02 | 2007-08-16 | Fuji Electric Device Technology Co Ltd | 半導体装置の製造方法 |
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2009
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Patent Citations (5)
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JP2002076326A (ja) * | 2000-09-04 | 2002-03-15 | Shindengen Electric Mfg Co Ltd | 半導体装置 |
JP2002368218A (ja) * | 2001-06-08 | 2002-12-20 | Sanyo Electric Co Ltd | 絶縁ゲート型半導体装置 |
JP2003243356A (ja) * | 2001-12-12 | 2003-08-29 | Denso Corp | 半導体装置の製造方法 |
JP2004281551A (ja) * | 2003-03-13 | 2004-10-07 | Toshiba Corp | 半導体基板及びその製造方法、半導体装置及びその製造方法、半導体パッケージ |
JP2007208074A (ja) * | 2006-02-02 | 2007-08-16 | Fuji Electric Device Technology Co Ltd | 半導体装置の製造方法 |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013201413A (ja) * | 2012-02-21 | 2013-10-03 | Rohm Co Ltd | 半導体装置および半導体装置の製造方法 |
US10741484B2 (en) | 2015-09-17 | 2020-08-11 | Semiconductor Components Industries, Llc | Stacked semiconductor device structure and method |
US9711434B2 (en) | 2015-09-17 | 2017-07-18 | Semiconductor Components Industries, Llc | Stacked semiconductor device structure and method |
US9893058B2 (en) | 2015-09-17 | 2018-02-13 | Semiconductor Components Industries, Llc | Method of manufacturing a semiconductor device having reduced on-state resistance and structure |
US10014245B2 (en) | 2015-09-17 | 2018-07-03 | Semiconductor Components Industries, Llc | Method for removing material from a substrate using in-situ thickness measurement |
US10163772B2 (en) | 2015-09-17 | 2018-12-25 | Semiconductor Components Industries, Llc | Stacked semiconductor device structure and method |
US11908699B2 (en) | 2015-09-17 | 2024-02-20 | Semiconductor Components Industries, Llc | Semiconductor packages with die including cavities |
US11342189B2 (en) | 2015-09-17 | 2022-05-24 | Semiconductor Components Industries, Llc | Semiconductor packages with die including cavities and related methods |
US11056589B2 (en) | 2016-12-27 | 2021-07-06 | Nuvoton Technology Corporation Japan | Semiconductor device |
US10854744B2 (en) | 2016-12-27 | 2020-12-01 | Panasonic Semiconductor Solutions Co., Ltd. | Semiconductor device |
US10541310B2 (en) | 2018-01-19 | 2020-01-21 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device and semiconductor module |
US10636885B2 (en) | 2018-01-19 | 2020-04-28 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device and semiconductor module |
JP2019129308A (ja) * | 2018-01-19 | 2019-08-01 | パナソニックIpマネジメント株式会社 | 半導体装置および半導体モジュール |
US10340347B1 (en) | 2018-01-19 | 2019-07-02 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device and semiconductor module |
JP6447946B1 (ja) * | 2018-01-19 | 2019-01-09 | パナソニックIpマネジメント株式会社 | 半導体装置および半導体モジュール |
JP2021015851A (ja) * | 2019-07-10 | 2021-02-12 | 株式会社東芝 | 半導体装置及び半導体装置の製造方法 |
JP7249898B2 (ja) | 2019-07-10 | 2023-03-31 | 株式会社東芝 | 半導体装置及び半導体装置の製造方法 |
US11532618B2 (en) | 2021-03-30 | 2022-12-20 | Kabushiki Kaisha Toshiba | Semiconductor device |
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