JP2010021532A - メサ型半導体装置及びその製造方法 - Google Patents
メサ型半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP2010021532A JP2010021532A JP2009121682A JP2009121682A JP2010021532A JP 2010021532 A JP2010021532 A JP 2010021532A JP 2009121682 A JP2009121682 A JP 2009121682A JP 2009121682 A JP2009121682 A JP 2009121682A JP 2010021532 A JP2010021532 A JP 2010021532A
- Authority
- JP
- Japan
- Prior art keywords
- mesa
- semiconductor layer
- oxide film
- type semiconductor
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 145
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 14
- 239000003822 epoxy resin Substances 0.000 claims description 7
- 229920000647 polyepoxide Polymers 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 238000009825 accumulation Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Thyristors (AREA)
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】メサ型半導体装置のメサ溝5内壁に熱酸化膜6からなる安定した保護膜を形成しPN接合部PNJCを被覆保護すると共に、N−型半導体層2の熱酸化膜6との界面に電子の蓄積層が形成されにくいように、メサ溝5内の熱酸化膜6で挟まれた空隙に負電荷を有する絶縁膜7を埋め込む。係る構成を採ることにより熱酸化膜6中の正電荷による影響を弱め熱酸化膜6との界面におけるN−型半導体層2への空乏層の拡がりを確保する。
【選択図】図5
Description
前記半導体基板の表面に、前記半導体基板よりも低濃度の第1導電型の第1の半導体層を形成する工程と、前記第1の半導体層の表面に第2導電型の第2の半導体層を形成する工程と、前記第2の半導体層の表面を部分的にマスク層で被覆して前記第2の半導体層の表面から前記半導体基板の中に到達するメサ溝を形成するエッチング工程と、前記メサ溝内及び前記第2の半導体層上に酸化膜を形成する工程と、前記メサ溝内の前記酸化膜で囲まれた溝内に有機絶縁膜を形成する工程と、を含むことを特徴とする。
PNJC PN接合部 4 ホトレジスト層 4A、6A,8A 開口部
5 メサ溝 6 熱酸化膜 7 絶縁膜 8 アノード電極
9 カソード電極 10 パッシベーション膜
11 PNJC部メサ溝側壁 12A,12B 酸化膜
14 ホトレジスト層 15 塗布ムラ 16 半導体ウエハ
101 N+型半導体基板 102 N−型半導体層
103 P型半導体層 105 絶縁膜 106 アノード電極
107 カソード電極 108 メサ溝 130 絶縁膜
Claims (8)
- 第1導電型の半導体基板を準備し、
前記半導体基板の表面に、前記半導体基板よりも低濃度の第1導電型の第1の半導体層を形成する工程と、
前記第1の半導体層の表面に第2導電型の第2の半導体層を形成する工程と、
前記第2の半導体層の表面を部分的にマスク層で被覆して前記第2の半導体層の表面から前記半導体基板の中に到達するメサ溝を形成するエッチング工程と、
前記メサ溝内及び前記第2の半導体層上に酸化膜を形成する工程と、
前記メサ溝内の前記酸化膜で囲まれた溝内に有機絶縁膜を形成する工程と、
を含むことを特徴とするメサ型半導体装置の製造方法。 - 第1導電型の半導体基板を準備し、
前記半導体基板の表面に、前記半導体基板よりも低濃度の第1導電型の第1の半導体層を形成する工程と、
前記第1の半導体層の表面に第2導電型の第2の半導体層を形成する工程と、
前記第2の半導体層の表面を部分的にマスク層で被覆して前記第2の半導体層の表面から前記半導体基板の中に到達するメサ溝を形成するエッチング工程と、
前記メサ溝内を埋設するように酸化膜を形成する工程と、
を含むことを特徴とするメサ型半導体装置の製造方法。 - 前記酸化膜上に有機絶縁膜を形成する工程を含むことを特徴とする請求項2に記載のメサ型半導体装置の製造方法。
- 前記有機絶縁膜が、有機レジスト、エポキシ樹脂であることを特徴とする請求項1または請求項3に記載のメサ型半導体装置の製造方法。
- 第1導電型の半導体基板と、
前記半導体基板の表面に接合され、前記半導体基板よりも低濃度の第1導電型の第1の半導体層と、
前記第1の半導体層の表面に接合され、前記第1の半導体層と共にPN接合部を形成する第2導電型の第2の半導体層と、
前記第2の半導体層の表面から前記半導体基板の中に到達するメサ溝と、
前記第2の半導体層上と前記メサ溝内に形成された酸化膜と、
前記メサ溝内の前記酸化膜で囲まれた溝内に形成された有機絶縁膜と、を備えることを特徴とするメサ型半導体装置。 - 第1導電型の半導体基板と、
前記半導体基板の表面に接合され、前記半導体基板よりも低濃度の第1導電型の第1の半導体層と、
前記第1の半導体層の表面に接合され、前記第1の半導体層と共にPN接合部を形成する第2導電型の第2の半導体層と、
前記第2の半導体層の表面から前記半導体基板の中に到達するメサ溝と、
前記前記メサ溝内に埋設された酸化膜と、を備えることを特徴とするメサ型半導体装置。 - 前記酸化膜上に有機絶縁膜を備えることを特徴とする請求項6に記載のメサ型半導体装置。
- 前記有機絶縁膜が有機レジスト、エポキシ樹脂からなることを特徴とする請求項5または請求項7に記載のメサ型半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009121682A JP2010021532A (ja) | 2008-06-12 | 2009-05-20 | メサ型半導体装置及びその製造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008153850 | 2008-06-12 | ||
JP2009121682A JP2010021532A (ja) | 2008-06-12 | 2009-05-20 | メサ型半導体装置及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2010021532A true JP2010021532A (ja) | 2010-01-28 |
Family
ID=41413965
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009121682A Pending JP2010021532A (ja) | 2008-06-12 | 2009-05-20 | メサ型半導体装置及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8319317B2 (ja) |
JP (1) | JP2010021532A (ja) |
KR (1) | KR101075784B1 (ja) |
CN (1) | CN101604660B (ja) |
TW (1) | TWI405268B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106098791A (zh) * | 2016-06-16 | 2016-11-09 | 杭州赛晶电子有限公司 | U型蚀刻直角台面硅二极管及其硅芯和制备方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009302222A (ja) * | 2008-06-12 | 2009-12-24 | Sanyo Electric Co Ltd | メサ型半導体装置及びその製造方法 |
DE102010046213B3 (de) * | 2010-09-21 | 2012-02-09 | Infineon Technologies Austria Ag | Verfahren zur Herstellung eines Strukturelements und Halbleiterbauelement mit einem Strukturelement |
CN103022088A (zh) * | 2011-09-21 | 2013-04-03 | 株式会社东芝 | 具有沟道结构体的半导体装置及其制造方法 |
US8809942B2 (en) * | 2011-09-21 | 2014-08-19 | Kabushiki Kaisha Toshiba | Semiconductor device having trench structure |
CN109904109B (zh) * | 2019-01-31 | 2021-05-28 | 上海朕芯微电子科技有限公司 | 一种双极集成电路的隔离结构及隔离结构的形成方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5432277A (en) * | 1977-08-15 | 1979-03-09 | Ibm | Method of forming silicon area isolated from dielectric |
JP2001177115A (ja) * | 1999-12-17 | 2001-06-29 | Matsushita Electronics Industry Corp | 高耐圧半導体装置 |
WO2008044801A1 (fr) * | 2006-10-13 | 2008-04-17 | Sanyo Electric Co., Ltd. | Dispositif semiconducteur et procédé de fabrication de celui-ci |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1485015A (en) | 1974-10-29 | 1977-09-08 | Mullard Ltd | Semi-conductor device manufacture |
US3973270A (en) | 1974-10-30 | 1976-08-03 | Westinghouse Electric Corporation | Charge storage target and method of manufacture |
JPS51139281A (en) * | 1975-05-28 | 1976-12-01 | Hitachi Ltd | Semi-conductor device |
US4179794A (en) | 1975-07-23 | 1979-12-25 | Nippon Gakki Seizo Kabushiki Kaisha | Process of manufacturing semiconductor devices |
US4389281A (en) * | 1980-12-16 | 1983-06-21 | International Business Machines Corporation | Method of planarizing silicon dioxide in semiconductor devices |
JPS57196585A (en) | 1981-05-28 | 1982-12-02 | Nec Corp | Manufacture of high-speed mesa type semiconductor device |
JPS5943545A (ja) * | 1982-09-06 | 1984-03-10 | Hitachi Ltd | 半導体集積回路装置 |
US4738936A (en) | 1983-07-01 | 1988-04-19 | Acrian, Inc. | Method of fabrication lateral FET structure having a substrate to source contact |
US4663832A (en) | 1984-06-29 | 1987-05-12 | International Business Machines Corporation | Method for improving the planarity and passivation in a semiconductor isolation trench arrangement |
US4725562A (en) * | 1986-03-27 | 1988-02-16 | International Business Machines Corporation | Method of making a contact to a trench isolated device |
US4775643A (en) | 1987-06-01 | 1988-10-04 | Motorola Inc. | Mesa zener diode and method of manufacture thereof |
KR940016546A (ko) | 1992-12-23 | 1994-07-23 | 프레데릭 얀 스미트 | 반도체 장치 및 제조방법 |
JP3492279B2 (ja) * | 2000-03-21 | 2004-02-03 | Necエレクトロニクス株式会社 | 素子分離領域の形成方法 |
US6383933B1 (en) * | 2000-03-23 | 2002-05-07 | National Semiconductor Corporation | Method of using organic material to enhance STI planarization or other planarization processes |
JP2002261269A (ja) | 2001-02-27 | 2002-09-13 | Matsushita Electric Ind Co Ltd | メサ型半導体装置の製造方法 |
JP3985582B2 (ja) | 2002-05-24 | 2007-10-03 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JP2005051111A (ja) | 2003-07-30 | 2005-02-24 | Matsushita Electric Ind Co Ltd | メサ型半導体装置 |
JP3767864B2 (ja) | 2004-02-16 | 2006-04-19 | ローム株式会社 | メサ型半導体装置の製法 |
JP4901300B2 (ja) | 2006-05-19 | 2012-03-21 | 新電元工業株式会社 | 半導体装置の製造方法 |
JP5117698B2 (ja) | 2006-09-27 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2009302222A (ja) | 2008-06-12 | 2009-12-24 | Sanyo Electric Co Ltd | メサ型半導体装置及びその製造方法 |
-
2009
- 2009-05-20 JP JP2009121682A patent/JP2010021532A/ja active Pending
- 2009-06-09 KR KR1020090051112A patent/KR101075784B1/ko not_active IP Right Cessation
- 2009-06-09 US US12/481,292 patent/US8319317B2/en active Active
- 2009-06-10 TW TW098119328A patent/TWI405268B/zh not_active IP Right Cessation
- 2009-06-12 CN CN200910140669.XA patent/CN101604660B/zh not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5432277A (en) * | 1977-08-15 | 1979-03-09 | Ibm | Method of forming silicon area isolated from dielectric |
JP2001177115A (ja) * | 1999-12-17 | 2001-06-29 | Matsushita Electronics Industry Corp | 高耐圧半導体装置 |
WO2008044801A1 (fr) * | 2006-10-13 | 2008-04-17 | Sanyo Electric Co., Ltd. | Dispositif semiconducteur et procédé de fabrication de celui-ci |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106098791A (zh) * | 2016-06-16 | 2016-11-09 | 杭州赛晶电子有限公司 | U型蚀刻直角台面硅二极管及其硅芯和制备方法 |
Also Published As
Publication number | Publication date |
---|---|
TW200952084A (en) | 2009-12-16 |
KR20090129346A (ko) | 2009-12-16 |
CN101604660A (zh) | 2009-12-16 |
KR101075784B1 (ko) | 2011-10-24 |
TWI405268B (zh) | 2013-08-11 |
US20090309193A1 (en) | 2009-12-17 |
CN101604660B (zh) | 2014-12-03 |
US8319317B2 (en) | 2012-11-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6673856B2 (ja) | 炭化珪素装置および炭化珪素装置の形成方法 | |
JP2009206502A (ja) | メサ型半導体装置及びその製造方法 | |
US10431491B2 (en) | Semiconductor device having a triple insulating film surrounded void | |
JP6028807B2 (ja) | 半導体装置及びその製造方法 | |
US9865680B2 (en) | Semiconductor device with peripheral void space and method of making the same | |
KR101075784B1 (ko) | 메사형 반도체 장치 및 그 제조 방법 | |
JP2018046251A (ja) | 半導体装置およびその製造方法 | |
US7772677B2 (en) | Semiconductor device and method of forming the same having a junction termination structure with a beveled sidewall | |
JP5074172B2 (ja) | メサ型半導体装置及びその製造方法 | |
JP2012235002A (ja) | 半導体装置およびその製造方法 | |
KR101075709B1 (ko) | 메사형 반도체 장치 및 그 제조 방법 | |
JP6103712B2 (ja) | 半導体装置およびそれを製造するための方法 | |
JP2011040431A (ja) | 半導体装置およびその製造方法 | |
JP2016035989A (ja) | 半導体装置 | |
US8610168B2 (en) | Semiconductor device and method of manufacturing the same | |
JP5074093B2 (ja) | 半導体装置及びその製造方法 | |
JP2010212440A (ja) | 半導体装置の製造方法 | |
JP2020021881A (ja) | 半導体装置 | |
CN109390387B (zh) | 半导体器件及其制造方法 | |
JP2020021882A (ja) | 半導体装置 | |
JP2009147248A (ja) | 半導体装置の製造方法 | |
JP2008147268A (ja) | メサ型半導体素子とその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20101215 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20110324 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20110603 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20110603 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120425 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20130207 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130215 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20130301 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130828 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130905 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140217 |