TWI405268B - 台型半導體裝置及其製造方法 - Google Patents
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Description
本發明係有關具有台溝的半導體裝置及其製造方法。本申請案中係將具有台溝的半導體裝置表示為台型半導體裝置。
習知技術中,就台型半導體裝置的一種類而言,已知有大功率用的台型二極體。茲參照第8圖及第9圖說明習知例的台型二極體。第8圖係顯示以矩陣狀配置複數個習知例的台型二極體之半導體晶圓的概略平面圖。第9圖係沿著第8圖之X-X線的剖面圖,顯示沿著切割線(scribe line)DL進行切塊(dicing)後的狀態。
於N+型半導體基板101的表面形成有N-型半導體層102。於N-型半導體層102的表面係形成有P型半導體層103,於P型半導體層103上係形成有第1絕緣膜105。此外,形成有與P型半導體層103電性連接的陽極電極106。
此外,形成有從P型半導體層103的表面到達N+型半導體基板101的台溝108。台溝108係形成為比N-型半導體102還深,台溝108的底部係位於N+型半導體基板101中。從P型半導體層103的表面至台溝108的底部,台溝108的側壁係具有順錐形狀呈傾斜。台型二極體係由該台溝108包圍而具有台型的構造。
此外,覆蓋台溝108的側壁而形成有由聚醯亞胺膜構成的第2絕緣膜130,且於N+型半導體基板101的背面形成有陰極電極107。
另外,關於台型的半導體裝置,記載於例如下述之專利文獻1。
專利文獻1:日本特開2003-347306號公報
雖然上述的習知例,顯示第9圖所示的第2絕緣膜130係以均勻的膜厚被覆著台溝108的內壁,但實際上係如第11圖所示,第2絕緣膜130係以在台溝108內壁的上部薄薄地形成並積存在台溝108的底部之形狀來形成。此種形狀係以下述的步驟形成。亦即,如第10圖所示,在進行滴塗(dispense)等而將第2絕緣膜130配置於台溝108時,係以第2絕緣膜130填埋台溝108內,惟由於在之後的熱處理時,進行醯亞胺化反應等,會使第2絕緣膜130的流動性變高,故全體而言第2絕緣膜130會流入台溝108的底部,以致如第11圖所示,第2絕緣膜130係在台溝108內壁的上部薄薄地形成。
故,在相當於電場強度最大的PN接合部PNJC之位置的台溝側壁110的第2絕緣膜130的膜厚變薄,而引起PN接合的耐壓劣化及漏電流的增大,結果即產生良率降低、可靠度降低等必須解決的嚴重課題。又,就解決上述問題的方法而言,雖然可採取重複若干次形成第2絕緣膜的方法,但其材料費用高,會使得半導體裝置的成本提高。
本發明的台型半導體裝置的製造方法係含有準備第1導電型的半導體基板,於前述半導體基板的表面形成比前述半導體基板低濃度的第1導電型的第1半導體層之步驟;於前述第1半導體層的表面形成第2導電型的第2半導體層之步驟;以遮罩層局部性地被覆前述第2半導體層的表面,並形成從前述第2半導體層的表面到達前述半導體基板中的台溝之蝕刻步驟;在前述台溝內及前述第2半導體層上形成氧化膜之步驟;及在前述台溝內的由前述氧化膜所圍成的溝內形成帶有負電荷的有機絕緣膜之步驟。
此外,本發明的台型半導體裝置係具備:第1導電型的半導體基板;第1導電型的第1半導體層,接合於前述半導體基板的表面且比前述半導體基板低濃度;第2導電型的第2半導體層,接合於前述第1半導體層的表面,與前述第1半導體層共同形成PN接合部;台溝,從前述第2半導體層的表面到達前述半導體基板中;氧化膜,形成在前述第2半導體層上及前述台溝內;及有機絕緣膜,形成在前述台溝內的由前述氧化膜所圍成的溝內且帶有負電荷。
在上述手段中係採用以良質的氧化膜被覆台溝內的PN接合部之平面(planar)製程技術,並利用被覆在氧化膜上的具有一定性質的絕緣膜來補強氧化膜的弱點。
依據本發明的台型半導體裝置及其製造方法,可藉廉價的材料使PN接合部的耐壓提升,並且能夠謀求漏電流的降低。
茲針對本發明實施形態的半導體裝置及其製造方法,以台型半導體裝置係台型二極體的情形為例進行說明。第1圖至第5圖係顯示本實施形態的台型二極體及其製造方法之剖面圖。其中,以下所說明的台型二極體的製造方法係針對以矩陣狀配置複數個台型二極體的晶圓狀半導體基板進行者,惟為了說明上的方便,僅圖示晶圓狀半導體基板所含有的複數個台型二極體之中的1個台型二極體。
如第1圖所示,準備擴散有高濃度的例如磷等N型雜質的N+型半導體基板1(例如,矽單晶基板)。使半導體層磊晶成長於該N+型半導體基板1的表面而形成低濃度的N型半導體層,亦即N-型半導體層2。另外,上述N+型與N-型之雙層結構亦可為進行下述步驟而得者,亦即,在從N-型半導體基板的兩面將作為雜質的磷等予以熱擴散而形成N+層後,進行化學性蝕刻或機械性研磨去除該半導體基板的一面。尤其在為必須具備較厚N-型半導體層2之超高耐壓品時,會有以擴散法比以磊晶法來形成之方式為理想之情形。
之後,在N-型半導體層2的表面擴散例如硼等P型雜質而形成P型半導體層3。藉此,於N-型半導體層2與P型半導體層3之界面形成PN接合部PNJC。在上述的構成中,N+型半導體基板1、N-型半導體層2、P型半導體層3之全體厚度例如約200μm左右。
接著,如第2圖所示,在P型半導體層3上形成具有開口部4A的光阻劑層4,該開口部4A係將預定形成台溝5之區域予以開口。接著,以該光阻劑層4為遮罩(mask),貫通P型半導體層3與N-型半導體層2將N+型半導體基板1予以乾蝕刻達至其厚度方向的中途之區域,藉此而形成台溝5。之後,使用氟酸、硝酸系的蝕刻液將因乾蝕刻而產生於台溝5側壁的損傷層(damage layer)去除。蝕刻結束後,以灰化(ashing)法或阻劑剝離液去除作為遮罩使用的光阻劑層4。
接著,如第3圖所示,在乾O2
或溼O2
環境的高溫爐中,於台溝5側壁上、P型半導體層3上、N+型半導體基板1上形成厚度數μm以下的熱氧化膜6。相當於PN接合部PNJC之位置的台溝側壁11係由該熱氧化膜6以可確保耐壓的足夠厚度所被覆保護,因此可容易解決以聚醯亞胺等填埋台溝5時之覆蓋台溝側壁11的膜厚形成為較薄而無法確保耐壓等之問題。惟本實施形態的台溝5的寬度係10μm以上,因此無法以熱氧化膜6填埋台溝5內全體,而形成由形成在台溝5內的熱氧化膜6所圍成的溝。
此時,在平面型NPN高耐壓電晶體中會出現成為問題的一種現象,亦即,會有在氧化膜的界面,於屬於集極層的N-型半導體層2形成電子蓄積層,空乏層未足夠擴展,在表面發生絕緣崩潰,而無法獲得以整體電阻率所決定的絕緣耐壓之現象,而在以熱氧化膜6被覆台溝5的台型二極體也會有發現該現象的情形。當為平面型電晶體時,從集極表面擴散若干個P+保護環(guard ring)來解決上述問題。而在台型二極體中將P+保護環設置在台溝5內則步驟數係增加,反而失去能夠以比平面型低廉地生產的好處。
因此,如第4圖所示,在台溝5內的由熱氧化膜6所圍成的溝內及除了之後形成陽極電極8的區域之外的P型半導體層3上的熱氧化膜6上形成絕緣膜7。當絕緣膜7係由環氧樹脂等所構成時,相較於疏水性的矽面直接露出之台溝5的溝內,環氧樹脂等係比較容易流入親水性的熱氧化膜6所圍成的溝內。在熱氧化膜6中,若熱氧化時於與N-型半導體層2等之界面的氧化膜側半導體為矽的話則會產生因過剩的矽所造成的陽離子,或者,產生存在於矽與氧化膜之界面的懸鍵(dangling bond)之界面態(interface state)。結果,熱氧化膜6整體成為或多或少帶有正電荷的狀態,若維持這種狀態,在與熱氧化膜6之界面的N-型半導體層2會蓄積電子,而成為耐壓降低的原因。
因此,為了抵消上述正電荷,形成於熱氧化膜6上的絕緣膜7係可選擇帶有負電荷之廉價的環氧樹脂。與其說由於絕緣膜7係隔介熱氧化膜6而形成於N-型半導體層2等上,因此絕緣膜7中的負電荷係直接對該N-型半導體層2等造成影響,不如說是起了減低熱氧化膜6的正電荷對N-型半導體層2等的影響之作用。另外,即使絕緣膜7中的負電荷量變多,抵消熱氧化膜6的正電荷量且成為以整體而言N-型半導體層2上存在負電荷之形式,只要台溝5內的N-型半導體層2的與熱氧化膜6之界面不反轉成P型便沒有問題。
結果,在N-型半導體層2與熱氧化膜6之界面的熱氧化膜6的正電荷所造成之N-型半導體層2的電子蓄積減少,空乏層變得容易擴展,因此發生在台溝側壁11的絕緣崩潰變得不易發生,耐壓便能夠接近整體電阻率所決定的值。當將由具有負電荷的環氧樹脂等所構成的絕緣膜7直接形成於台溝5上時,亦防止在N-型半導體層2的與絕緣膜7之界面的P型反轉層所產生的漏電流等之問題。
另外,在本實施形態中,雖然亦將絕緣膜7形成在台溝5以外的部分,但只要填埋比台溝5的相當於PNJC部之位置的台溝側壁11下部的台溝5的話,便可獲得上述效果。惟當未將台溝5以絕緣膜7完全填埋時,形成陽極電極8時等的藥液等會殘留於台溝5內而引起可靠度方面的問題,且如第7圖所示產生半導體晶圓16內的光阻劑層14的塗佈不均15,有造成良率下降之虞,因此較理想為將台溝5完全填埋。
另外,就前述絕緣膜7而言,亦可使用例如所謂的永久阻劑之有機阻劑膜與聚醯亞胺膜、或者無機或有機的SOG(Spin On Glass;旋覆式玻璃)膜、或者氮化矽膜等。
最後,如第5圖所示,經預定的微影步驟而在熱氧化膜6形成用以進行P型半導體層與後述的陽極電極8之接觸的開口部6A。此時亦去除形成於N+型半導體基板側1的熱氧化膜6。之後,藉由濺鍍法或蒸鍍法將鋁等導電材料形成在P型半導體層3上等,再經預定的步驟而形成陽極電極8,並在N+型半導體基板1上形成陰極電極9,藉此便完成以簡便且具穩定性的熱氧化膜6及由廉價的環氧樹脂等所等所構成的絕緣膜7來填埋台溝5的台型二極體。
另外,如第6圖所示,依需要而將以電漿CVD法製得的氮化膜所構成的鈍化(passivation)膜10以在陽極電極8上具有開口部8A之狀態予以形成,能夠有效地謀求可靠度的提升。當如前述僅在台溝5內填埋絕緣膜7而達成初期目的時,將鈍化膜10亦形成為比台溝5的寬度稍微大的寬度,藉此,可阻止絕緣膜7中的負電荷量的變化,而能夠獲得可靠度高的台型二極體。
以下,參照第12圖(A)及第12圖(B)說明本發明的其他實施形態。又,其他實施形態的特徵係在於僅以氧化膜填埋台溝5內。
首先,第12圖(A)所示構成與第6圖所示構成之相異點,係在以前述熱氧化膜6、及CVD法所製作的氧化膜12A完全填埋在台溝5內的狀態下,在該等膜之上形成前述絕緣膜7之點。其他的構成則與第6圖相同。
再者,第12圖(B)所示構成與第6圖所示構成之相異點,係在僅以由CVD法所製作的氧化膜12B完全填埋在台溝5內的狀態下,在其上形成前述絕緣膜7之點。其他構成則與第6圖相同。
在本實施形態中,係以台溝5深度約100μm、台溝5寬度約10μm為例加以說明,惟前述台溝5的深度、寬度尺寸可做種種變更,且對應各種尺寸形成在台溝內的氧化膜之構成可做變更。亦即,對於比前述寬度尺寸小的台溝要形成氧化膜時,亦可僅以熱氧化膜完全填埋在台溝5內,以取代第12圖(B)所示的氧化膜12B,而可建構更簡便的製程,例如,寬度尺寸若在5μm以下,則可僅以熱氧化膜填埋。此種情況時,為了確保台型二極體的超高耐壓、低漏電流特性,而為了將熱氧化膜6的成長速度減緩以謀求減少氧化膜中的因過剩的矽所造成的正電荷,並且依需要而減少產生於N-型半導體層2與熱氧化膜6之界面的懸鍵亦可藉由採用氫退火等,來使熱氧化膜所具有的正電荷量減少。另外,雖以台型二極體為一例來說明本發明,但本發明亦可廣泛應用於台型電晶體等其他台型半導體裝置。
1、101...N+型半導體基板
2、102...N-型半導體層
3、103...P型半導體層
4、14...光阻劑層
4A、6A、8A...開口部
5、108...台溝
6...熱氧化膜
7、105、130...絕緣膜
8、106...陽極電極
9、107...陰極電極
10...鈍化膜
11...PNJC部台溝側壁
12A、12B...氧化膜
15...塗佈不均
16...半導體晶圓
DL...切割線
PNJC...PN接合部
第1圖係顯示本發明實施形態的台型二極體及其製造方法之剖面圖。
第2圖係顯示本發明實施形態的台型二極體及其製造方法之剖面圖。
第3圖係顯示本發明實施形態的台型二極體及其製造方法之剖面圖。
第4圖係顯示本發明實施形態的台型二極體及其製造方法之剖面圖。
第5圖係顯示本發明實施形態的台型二極體及其製造方法之剖面圖。
第6圖係顯示本發明實施形態的台型二極體及其製造方法之剖面圖。
第7圖係顯示在具有未被絕緣膜填埋的台溝之半導體晶圓上所形成的光阻劑層的塗佈不均之平面圖。
第8圖係顯示習知例的台型二極體及其製造方法之平面圖。
第9圖係習知例的台型二極體的剖面圖。
第10圖係顯示習知例的台型二極體及其製造方法之剖面圖。
第11圖係顯示習知例的台型二極體及其製造方法之剖面圖。
第12圖(A)及(B)係顯示本發明其他實施形態的台型二極體及其製造方法之剖面圖。
1...N+型半導體基板
2...N-型半導體層
3...P型半導體層
5...台溝
6...熱氧化膜
6A...開口部
7...絕緣膜
8...陽極電極
9...陰極電極
11...PNJC部台溝側壁
Claims (6)
- 一種台型半導體裝置的製造方法,係含有:準備第1導電型的半導體基板,於前述半導體基板的表面形成比前述半導體基板低濃度的第1導電型的第1半導體層之步驟;於前述第1半導體層的表面形成第2導電型的第2半導體層之步驟;以遮罩層局部性地被覆前述第2半導體層的表面,並形成從前述第2半導體層的表面到達前述半導體基板中的台溝之蝕刻步驟;在前述台溝內及前述第2半導體層上形成氧化膜之步驟;及在由前述台溝內的前述氧化膜所圍成的溝內形成帶有負電荷的有機絕緣膜之步驟。
- 一種台型半導體裝置的製造方法,係含有:準備第1導電型的半導體基板,於前述半導體基板的表面形成比前述半導體基板低濃度的第1導電型的第1半導體層之步驟;於前述第1半導體層的表面形成第2導電型的第2半導體層之步驟;以遮罩層局部性地被覆前述第2半導體層的表面,並形成從前述第2半導體層的表面到達前述半導體基板中的台溝之蝕刻步驟;以埋設於前述台溝內的方式形成氧化膜之步驟; 及在前述氧化膜上形成帶有負電荷的有機絕緣膜之步驟。
- 如申請專利範圍第1項或第2項之台型半導體裝置的製造方法,其中,前述有機絕緣膜係有機阻劑、環氧樹脂。
- 一種台型半導體裝置,係具備:第1導電型的半導體基板;第1導電型的第1半導體層,接合於前述半導體基板的表面且比前述半導體基板低濃度;第2導電型的第2半導體層,接合於前述第1半導體層的表面,與前述第1半導體層共同形成PN接合部;台溝,從前述第2半導體層的表面到達前述半導體基板中;氧化膜,形成在前述第2半導體層上及前述台溝內;及有機絕緣膜,形成在前述台溝內的由前述氧化膜所圍成的溝內且帶有負電荷。
- 一種台型半導體裝置,係具備:第1導電型的半導體基板;第1導電型的第1半導體層,接合於前述半導體基板的表面且比前述半導體基板低濃度;第2導電型的第2半導體層,接合於前述第1半 導體層的表面,與前述第1半導體層共同形成PN接合部;台溝,從前述第2半導體層的表面到達前述半導體基板中;氧化膜,埋設於前述台溝內;及有機絕緣膜,形成在前述氧化膜上且帶有負電荷。
- 如申請專利範圍第4項或第5項之台型半導體裝置,其中,前述有機絕緣膜係由有機阻劑、環氧樹脂所構成。
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KR101075784B1 (ko) | 2011-10-24 |
US20090309193A1 (en) | 2009-12-17 |
CN101604660A (zh) | 2009-12-16 |
TW200952084A (en) | 2009-12-16 |
KR20090129346A (ko) | 2009-12-16 |
CN101604660B (zh) | 2014-12-03 |
JP2010021532A (ja) | 2010-01-28 |
US8319317B2 (en) | 2012-11-27 |
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