JP2009004496A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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Abstract
【解決手段】半導体基板1は第1主面に溝1bを有している。絶縁ゲート型電界効果部は、第1主面に形成されたゲート電極12aを含んでいる。電位固定用電極12bは、溝1b内を埋め込み、かつ第1主面上で溝1bの幅w1よりも大きい幅w2となるように張り出した張り出し部を有している。エミッタ電極は、第1主面上に形成され、ゲート電極12aと電気的に絶縁され、かつ電位固定用電極12bの張り出し部の上面全体に接続されている。
【選択図】図1
Description
半導体基板の主面に溝が形成される。溝内を埋め込むように主面上に導電層が形成される。導電層をパターニングすることにより、溝内を埋め込み、かつ主面上で溝の幅よりも大きい幅となるように張り出した張り出し部を有する電位固定用電極が形成されるとともに、主面にゲート電極が形成される。ゲート電極上を覆い、かつ電位固定用電極の張り出し部を露出するように絶縁層が形成される。ゲート電極と電気的に絶縁し、かつ電位固定用電極の張り出し部の上面全体に接続するように主電極が形成される。
(実施の形態1)
図1は、本発明の実施の形態1における半導体装置の構成を概略的に示す断面図である。図1を参照して、本実施の形態の半導体装置は、たとえば縦型や横型のMOSFET(Metal Oxide Semiconductor Field Effect Transistor)、IGBTなどに適用され得る。
図2〜図11は、本発明の実施の形態1における半導体装置の製造方法を工程順に示す概略断面図である。図2を参照して、n-領域2を有する半導体基板1の第1主面にp型領域3とn型領域4とが形成される。次に、これらのn型領域4とp型領域3との双方を突き抜けてn-領域2に達する溝1aと、n型領域4が形成されていない領域においてp型領域3を突き抜けてn-領域2に達する溝1bとが、半導体基板1の第1主面に形成される。溝1a、1bの内壁面および半導体基板1の第1主面を覆うように絶縁膜11が形成される。この絶縁膜11は、たとえば熱酸化法により形成されたシリコン酸化膜、CVD(Chemical Vapor Deposition)法により形成されたシリコン酸化膜またはシリコン窒化膜、またはそれらの組み合わせの材質よりなる。
図6を参照して、半導体基板1の第1主面上を覆うように絶縁膜13が形成される。この絶縁膜13は、常圧CVD法やプラズマCVD法により形成されたPSG(Phospho Silicate Glass)、BPSG(Boro-Phospho Silicate Glass)、BP(Boro-Phospho)−TEOS(Tetra-Ethyl-Ortho-Silicate)シリコン酸化膜などのいずれでもよい。
図1に示した構成は、図13〜図15に示す縦型のIGBTや、図16に示す縦型のnチャネルMOSFET(以下、nMOSFETと称する)や、図17に示すような横型のIGBTなどに適用することができる。
図1に示す上記の実施の形態1においては、絶縁ゲート型電界効果部のゲートがトレンチゲート構造のものについて説明したが、絶縁ゲート型電界効果部のゲートは平面ゲート構造であってもよい。以下、その構成について説明する。
実施の形態1〜3においてはIGBT、MOSFETについて説明したが、本発明は、これ以外の絶縁ゲート型電界効果部を有する素子に適用することができ、たとえばキャリア蓄積型IGBT、MCT(MOS-Controlled Thyristor)、IEGT(Injection Enhanced Gate Transistor)などにも適用することができる。以下、これらの構成について説明する。
エミッタ領域の形状を変えた他の例について説明する。
今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。
Claims (8)
- 第1主面を有し、前記第1主面に溝を有する半導体基板と、
前記第1主面に形成されたゲート電極を含む絶縁ゲート型電界効果部を有する素子と、
前記溝内を埋め込み、かつ前記第1主面上で前記溝の幅よりも大きい幅となるように張り出した張り出し部を有する電位固定用電極と、
前記第1主面上に形成され、前記ゲート電極と電気的に絶縁され、かつ前記電位固定用電極の前記張り出し部の上面全体に接続された第1の主電極と
を備えた、半導体装置。 - 前記第1の主電極は、
第1の金属膜と、
前記第1の金属膜上に形成され、かつ前記第1の金属膜よりも低融点で、かつ前記半導体基板の構成材料と反応しやすい第2の金属膜と
を含む、請求項1に記載の半導体装置。 - 前記素子は、前記絶縁ゲート型電界効果部を有するバイポーラトランジスタである、請求項1または2に記載の半導体装置。
- 前記半導体基板は、前記第1主面と対向する第2主面を有し、
前記第2主面に形成された第2の主電極をさらに備え、
前記素子は、前記第1の主電極と前記第2の主電極との間で主電流が流れる縦型素子である、請求項1〜3のいずれかに記載の半導体装置。 - 前記第1主面に形成された第2の主電極をさらに備え、
前記素子は、前記第1の主電極と前記第2の主電極との間で主電流が流れる横型素子である、請求項1〜3のいずれかに記載の半導体装置。 - 半導体基板の主面に溝を形成する工程と、
前記溝内を埋め込むように前記主面上に導電層を形成する工程と、
前記導電層をパターニングすることにより、前記溝内を埋め込み、かつ前記主面上で前記溝の幅よりも大きい幅となるように張り出した張り出し部を有する電位固定用電極を形成するとともに、前記主面にゲート電極を形成する工程と、
前記ゲート電極上を覆い、かつ前記電位固定用電極の前記張り出し部を露出するように絶縁層を形成する工程と、
前記ゲート電極と電気的に絶縁し、かつ前記電位固定用電極の前記張り出し部の上面全体に接続するように主電極を形成する工程と
を備えた、半導体装置の製造方法。 - 前記主電極を形成する工程は、
前記電位固定用電極の前記張り出し部に接するように第1の金属膜を形成する工程と、
前記第1の金属膜よりも低融点で、かつ前記半導体基板の構成材料と反応しやすい材質よりなる第2の金属膜を前記第1の金属膜上に形成する工程と
を備えた、請求項6に記載の半導体装置の製造方法。 - 前記第1および第2の金属膜を安定化させるための熱処理を施す工程をさらに備えた、請求項7に記載の半導体装置の製造方法。
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CNA2008100812352A CN101330101A (zh) | 2007-06-20 | 2008-02-20 | 半导体装置及其制造方法 |
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