JP2008166744A - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- JP2008166744A JP2008166744A JP2007313006A JP2007313006A JP2008166744A JP 2008166744 A JP2008166744 A JP 2008166744A JP 2007313006 A JP2007313006 A JP 2007313006A JP 2007313006 A JP2007313006 A JP 2007313006A JP 2008166744 A JP2008166744 A JP 2008166744A
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Abstract
【解決手段】支持基板上に絶縁層、島状のシリコン層が順に積層されたSOI基板と、島状のシリコン層の一表面上及び側面に設けられたゲート絶縁層と、ゲート絶縁層を介して島状のシリコン層上に設けられたゲート電極と、を有する構造とする。このとき、ゲート絶縁層は、島状のシリコン層の一表面上と比較して、島状のシリコン層の側面と接する領域の誘電率を小さくする。
【選択図】図1
Description
図1は、本発明に係る半導体装置の主要な構成を説明するための上面図及び断面図である。図1は、特に薄膜トランジスタの構成を示しており、図1(A)は上面図、図1(B)は図1(A)における破線O−P間の断面図、図1(C)は図1(A)における破線Q−R間の断面図を示している。なお、図1(A)は、一部薄膜等を省略している。
本実施の形態では、上記実施の形態1と異なる作製方法で半導体装置を作製する例について、図4乃至図6を用いて説明する。
本実施の形態では、上記実施の形態と異なる作製方法で半導体装置を作製する例について、図7乃至図9を用いて説明する。
本実施の形態では、上記実施の形態と異なる作製方法で半導体装置を作製する例について、図10、図11を用いて説明する。
本実施の形態では、上記実施の形態と異なる作製方法で半導体装置を作製する例について、図13乃至図15を用いて説明する。
本発明に係る半導体装置は、CPU(中央演算回路:Central Processing Unit)等の集積回路に適用することができる。本実施の形態では、図19に示した半導体装置を適用したCPUの例に関して、図面を用いて以下に説明する。
本実施の形態では、上記実施の形態で示した半導体装置の使用形態の一例について説明する。具体的には、非接触でデータの入出力が可能である半導体装置の適用例に関して、図面を用いて以下に説明する。非接触でデータの入出力が可能である半導体装置は利用の形態によって、RFIDタグ、IDタグ、ICタグ、ICチップ、RFタグ、無線タグ、電子タグまたは無線チップとも呼ばれる。
102 絶縁層
104 シリコン層
105 SOI基板
106 シリコン層
107 絶縁層
108 絶縁層
110 絶縁層
112 導電層
114 チャネル形成領域
116 不純物領域
120 薄膜トランジスタ
Claims (21)
- 支持基板上に絶縁層、島状のシリコン層が順に積層されたSOI基板と、
前記島状のシリコン層の一表面上及び側面に設けられたゲート絶縁層と、
前記ゲート絶縁層を介して前記島状のシリコン層上に設けられ、前記島状のシリコン層を横断するように設けられたゲート電極と、
を有し、
前記ゲート絶縁層は、前記島状のシリコン層の一表面上と比較して、前記島状のシリコン層の側面と接する領域の誘電率が小さいことを特徴とする半導体装置。 - 支持基板上に絶縁層、島状のシリコン層が順に積層されたSOI基板と、
前記島状のシリコン層の一表面上及び側面に設けられたゲート絶縁層と、
前記ゲート絶縁層を介して前記島状のシリコン層上に設けられ、前記島状のシリコン層を横断するように設けられたゲート電極と、
を有し、
前記ゲート絶縁層は、少なくとも前記ゲート電極と重なる領域において、前記島状のシリコン層の一表面上と比較して、前記島状のシリコン層の側面と接する領域の誘電率が小さいことを特徴とする半導体装置。 - 支持基板上に絶縁層、島状のシリコン層が順に積層されたSOI基板と、
前記島状のシリコン層の一表面上及び側面に設けられたゲート絶縁層と、
前記ゲート絶縁層を介して前記島状のシリコン層上に設けられ、前記島状のシリコン層を横断するように設けられたゲート電極と、
を有し、
前記ゲート絶縁層は、前記島状のシリコン層の一表面上と比較して、前記島状のシリコン層の側面と接する領域の厚さが厚く、且つ、誘電率が小さいことを特徴とする半導体装置。 - 支持基板上に絶縁層、島状のシリコン層が順に積層されたSOI基板と、
前記島状のシリコン層の一表面上及び側面に設けられたゲート絶縁層と、
前記ゲート絶縁層を介して前記島状のシリコン層上に設けられ、前記島状のシリコン層を横断するように設けられたゲート電極と、
を有し、
前記ゲート絶縁層は、少なくとも前記ゲート電極と重なる領域において、前記島状のシリコン層の一表面上と比較して、前記島状のシリコン層の側面と接する領域の厚さが厚く、且つ、誘電率が小さいことを特徴とする半導体装置。 - 請求項3又は請求項4において、
前記ゲート絶縁層において、前記島状のシリコン層の一表面上の厚さをt1、前記島状のシリコン層の側面と接する領域の厚さをt2とし、t1<t2≦3t1を満たすことを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一において、
前記島状のシリコン層の一表面上及び側面に設けられたゲート絶縁層は、
前記島状のシリコン層の一表面上に接して設けられた第1の絶縁層と、
前記島状のシリコン層の側面と接して設けられた第2の絶縁層と、
を有することを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一において、
前記島状のシリコン層の一表面上及び側面に設けられたゲート絶縁層は、
前記島状のシリコン層の一表面上に設けられた第1の絶縁層と、
前記島状のシリコン層の側面に設けられた第2の絶縁層及び第3の絶縁層と、
を有することを特徴とする半導体装置。 - 請求項1乃至請求項7のいずれか一において、
前記島状のシリコン層の端部は、テーパ角が45°以上95°未満であることを特徴とする半導体装置。 - 請求項1乃至請求項8のいずれか一において、
前記SOI基板はSIMOX基板であることを特徴とする半導体装置。 - 請求項1乃至請求項8のいずれか一において、
前記SOI基板は貼り合わせ基板であることを特徴とする半導体装置。 - SOI基板のシリコン層を島状に形成し、
前記島状のシリコン層の一表面上及び側面に接して第1の絶縁層を形成し、
前記第1の絶縁層を前記島状のシリコン層の一表面が露出するまで選択的に除去して、前記島状のシリコン層の側面と接する第2の絶縁層を形成し、
前記島状のシリコン層の一表面及び前記第2の絶縁層に接して第3の絶縁層を形成し、
前記第3の絶縁層を介して前記島状のシリコン層の一表面上に、前記島状のシリコン層を横断するようにゲート電極層を形成することを特徴とする半導体装置の作製方法。 - 請求項11において、
前記島状のシリコン層は、端部のテーパ角が45°以上95°未満となるように形成することを特徴とする半導体装置の作製方法。 - SOI基板のシリコン層を島状に形成して第1のシリコン層を形成し、
前記第1のシリコン層の一表面及び側面に接して第1の絶縁層を形成し、
前記第1の絶縁層を前記島状の第1のシリコン層の一表面が露出するまで選択的に除去して、前記第1のシリコン層の側面と接する第2の絶縁層を形成するとともに、前記第1のシリコン層の上層に非晶質領域を形成し、
前記第1のシリコン層に形成された非晶質領域を除去して島状の第2のシリコン層を形成し、
前記第2のシリコン層及び前記第2の絶縁層に接して第3の絶縁層を形成し、
前記第3の絶縁層を介して前記第2のシリコン層の一表面上に、前記第2のシリコン層を横断するようにゲート電極層を形成することを特徴とする半導体装置の作製方法。 - SOI基板のシリコン層を島状に形成して第1のシリコン層を形成し、
前記第1のシリコン層の一表面及び側面に接して第1の絶縁層を形成し、
垂直方向を主体とした異方性エッチングにより、前記第1のシリコン層及び前記第1の絶縁層を薄膜化して、島状の第2のシリコン層及び前記第2のシリコン層の側面と接する第2の絶縁層を形成し、
前記第2のシリコン層及び前記第2の絶縁層に接して第3の絶縁層を形成し、
前記第3の絶縁層を介して前記第2のシリコン層の一表面上に、前記第2のシリコン層を横断するようにゲート電極層を形成することを特徴とする半導体装置の作製方法。 - 請求項11又は請求項12において、
前記第1のシリコン層は、膜厚60nm乃至70nmの範囲で形成し、
前記第2のシリコン層は、膜厚20nm乃至30nmの範囲で形成することを特徴とする半導体装置の作製方法。 - 請求項13乃至請求項15のいずれか一において、
前記第2のシリコン層は、端部のテーパ角が45°以上95°未満となるように形成することを特徴とする半導体装置の作製方法。 - 請求項11乃至請求項16のいずれか一において、
前記第2の絶縁層及び前記第3の絶縁層は、ゲート絶縁層として形成することを特徴とする半導体装置の作製方法。 - 請求項11乃至請求項17のいずれか一において、
前記第2の絶縁層は、前記第3の絶縁層と比較して誘電率が小さい層を形成することを特徴とする半導体装置の作製方法。 - 請求項11乃至請求項18のいずれか一において、
前記ゲート電極層を形成した後、熱処理を行うことを特徴とする半導体装置の作製方法。 - 請求項11乃至請求項19のいずれか一において、
前記SOI基板はSIMOX法で形成される基板を用いることを特徴とする半導体装置の作製方法。 - 請求項11乃至請求項19のいずれか一において、
前記SOI基板は貼り合わせ法で形成される基板を用いることを特徴とする半導体装置の作製方法。
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- 2007-12-04 JP JP2007313006A patent/JP5348874B2/ja not_active Expired - Fee Related
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JP2016028427A (ja) * | 2008-09-12 | 2016-02-25 | 株式会社半導体エネルギー研究所 | 半導体装置、表示装置及び液晶表示装置 |
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JP2016527709A (ja) * | 2013-06-10 | 2016-09-08 | レイセオン カンパニー | カラムiii−vアイソレーション領域を有する半導体構造 |
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US7968884B2 (en) | 2011-06-28 |
JP5348874B2 (ja) | 2013-11-20 |
US20080128808A1 (en) | 2008-06-05 |
CN101197394B (zh) | 2012-07-04 |
KR20080052428A (ko) | 2008-06-11 |
JP5685297B2 (ja) | 2015-03-18 |
JP2015073138A (ja) | 2015-04-16 |
JP5973598B2 (ja) | 2016-08-23 |
US20110254004A1 (en) | 2011-10-20 |
CN101197394A (zh) | 2008-06-11 |
JP2013254980A (ja) | 2013-12-19 |
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