JP2008135521A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2008135521A JP2008135521A JP2006319910A JP2006319910A JP2008135521A JP 2008135521 A JP2008135521 A JP 2008135521A JP 2006319910 A JP2006319910 A JP 2006319910A JP 2006319910 A JP2006319910 A JP 2006319910A JP 2008135521 A JP2008135521 A JP 2008135521A
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 165
- 238000004519 manufacturing process Methods 0.000 title claims description 41
- 239000003566 sealing material Substances 0.000 claims abstract description 97
- 239000000463 material Substances 0.000 claims abstract description 47
- 229910000679 solder Inorganic materials 0.000 claims abstract description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 53
- 239000011889 copper foil Substances 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 43
- 229920005989 resin Polymers 0.000 claims description 23
- 239000011347 resin Substances 0.000 claims description 23
- 229920001187 thermosetting polymer Polymers 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 17
- 239000008393 encapsulating agent Substances 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 7
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- 229920001721 polyimide Polymers 0.000 claims description 4
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- 239000003822 epoxy resin Substances 0.000 description 13
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- 238000010438 heat treatment Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 238000003825 pressing Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
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- 238000001816 cooling Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
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- 230000005496 eutectics Effects 0.000 description 1
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- 238000007747 plating Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
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Abstract
【解決手段】 ソルダーレジスト等からなる下層絶縁膜1の上面には配線2が設けられている。半導体構成体6は、その突起電極12が配線2にボンディングされていることにより、配線2上にフェースダウン方式により搭載されている。半導体構成体6と配線2を含む下層絶縁膜1との間およびその周囲にはアンダーフィル材13が設けられている。半導体構成体6、アンダーフィル材13および配線2を含む下層絶縁膜1の上面には封止材14が設けられている。配線2の接続パッド部下には半田ボール5が設けられている。この場合、両面配線2構造で上下導通部を有する比較的高価なインターポーザを用いていないため、コストを低減することができ、また薄型化することができる。
【選択図】 図1
Description
請求項2に記載の発明に係る半導体装置は、請求項1に記載の発明において、前記配線、前記アンダーフィル材および前記封止材の下面に、前記配線の接続パッド部に対応する部分に開口部を有する下層絶縁膜が設けられていることを特徴とするものである。
請求項3に記載の発明に係る半導体装置は、請求項2に記載の発明において、前記下層絶縁膜の開口部内およびその下方に半田ボールが前記配線の接続パッド部に接続されて設けられていることを特徴とするものである。
請求項4に記載の発明に係る半導体装置は、請求項1〜3のいずれかに記載の発明において、前記封止材の上面に放熱層が設けられていることを特徴とするものである。
請求項5に記載の発明に係る半導体装置は、請求項1〜3のいずれかに記載の発明において、前記封止材の上面に上層配線が前記半導体構成体の周囲における前記封止材中に設けられた上下導通部を介して前記配線に接続されて設けられていることを特徴とするものである。
請求項6に記載の発明に係る半導体装置は、請求項5に記載の発明において、前記上層配線を含む前記封止材の上面にオーバーコート膜が設けられていることを特徴とするものである。
請求項7に記載の発明に係る半導体装置は、請求項1〜3のいずれかに記載の発明において、前記配線は銅箔からなることを特徴とするものである。
請求項8に記載の発明に係る半導体装置は、請求項1〜3のいずれかに記載の発明において、前記封止材は基材に熱硬化性樹脂を含浸させたものからなることを特徴とするものである。
請求項9に記載の発明に係る半導体装置の製造方法は、配線形成用銅箔の下面に剥離層およびベース板が設けられたものを用意する工程と、前記配線形成用銅箔をパターニングして配線を形成する工程と、半導体基板および該半導体基板下に設けられた複数の外部接続用電極を有する半導体構成体の外部接続用電極を前記配線にボンディングする工程と、前記半導体構成体全体および前記配線の少なくとも一部を封止材で覆う工程と、前記ベース板および前記剥離層を除去する工程と、を有することを特徴とするものである。
請求項10に記載の発明に係る半導体装置の製造方法は、請求項9に記載の発明において、前記半導体構成体と前記配線を含む前記剥離層との間にアンダーフィル材を形成する工程を有することを特徴とするものである。
請求項11に記載の発明に係る半導体装置の製造方法は、請求項10に記載の発明において、前記ベース板および前記剥離層の除去により露出された前記配線、前記アンダーフィル材および前記封止材の下面に、前記配線の接続パッド部に対応する部分に開口部を有する下層絶縁膜を形成する工程を有することを特徴とするものである。
請求項12に記載の発明に係る半導体装置の製造方法は、請求項11に記載の発明において、前記下層絶縁膜を形成する工程後に、前記下層絶縁膜の開口部内およびその下方に半田ボールを前記配線の接続パッド部に接続させて形成する工程を有することを特徴とするものである。
請求項13に記載の発明に係る半導体装置の製造方法は、請求項9〜12のいずれかに記載の発明において、前記封止材を形成する工程は、前記半導体構成体の周囲における前記配線を含む前記剥離層上に、前記半導体構成体に対応する部分に開口部を有する第1の封止材形成用シート、第2の封止材形成用シートおよび銅箔を配置し、上下から加熱加圧して、前記半導体構成体、前記アンダーフィル材および前記配線を含む前記剥離層上に封止材を形成し、且つ、前記封止材上に前記銅箔を固着する工程であることを特徴とするものである。
請求項14に記載の発明に係る半導体装置の製造方法は、請求項13に記載の発明において、前記封止材上に固着された前記銅箔を除去する工程を有することを特徴とするものである。
請求項15に記載の発明に係る半導体装置の製造方法は、請求項13に記載の発明において、前記封止材上に固着された前記銅箔により放熱層を形成する工程を有することを特徴とするものである。
請求項16に記載の発明に係る半導体装置の製造方法は、請求項13に記載の発明において、前記第1、第2の封止材形成用シートは基材に熱硬化性樹脂を含浸させたものからなることを特徴とするものである。
請求項17に記載の発明に係る半導体装置の製造方法は、請求項9〜12のいずれかに記載の発明において、前記封止材を形成する工程は、前記半導体構成体の周囲における前記配線を含む前記剥離層上に、前記半導体構成体に対応する部分に開口部を有する第1の封止材形成用シート、前記半導体構成体に対応する部分に開口部を有し且つ下側上下導通部を有する第2の封止材形成用シート、第3の封止材形成用シートおよび下面に上側上下導通部を有する上層配線形成用銅箔を配置し、上下から加熱加圧して、前記半導体構成体、前記アンダーフィル材および前記配線を含む前記剥離層上に封止材を形成し、且つ、前記半導体構成体の周囲における前記封止材中に前記下側上下導通部および前記上側上下導通部からなる上下導通部を形成し、さらに、前記封止材上に前記上層配線形成用銅箔を前記上下導通部を介して前記配線に接続させて固着する工程であることを特徴とするものである。
請求項18に記載の発明に係る半導体装置の製造方法は、請求項17に記載の発明において、前記封止材上に固着された前記上層配線形成用銅箔をパターニングして上層配線を形成する工程を有することを特徴とするものである。
請求項19に記載の発明に係る半導体装置の製造方法は、請求項18に記載の発明において、前記上層配線を含む前記封止材の上面にオーバーコート膜を形成する工程を有することを特徴とするものである。
請求項20に記載の発明に係る半導体装置の製造方法は、請求項17に記載の発明において、前記第1、第2、第3の封止材形成用シートは基材に熱硬化性樹脂を含浸させたものからなることを特徴とするものである。
請求項21に記載の発明に係る半導体装置の製造方法は、請求項9〜12のいずれかに記載の発明において、前記ベース板は銅箔からなることを特徴とするものである。
請求項22に記載の発明に係る半導体装置の製造方法は、請求項21に記載の発明において、前記剥離層はポリイミドフィルムからなることを特徴とするものである。
図1はこの発明の第1実施形態としての半導体装置の断面図を示す。この半導体装置はソルダーレジスト等からなる平面方形状の下層絶縁膜1を備えている。下層絶縁膜1の上面には銅箔からなる複数の配線2が設けられている。配線2の一端部の接続パッド部上面には錫メッキからなる表面処理層3が設けられている。配線2の他端部の接続パッド部に対応する部分における下層絶縁膜1には開口部4が設けられている。下層絶縁膜1の開口部4内およびその下方には半田ボール5が配線2の他端部の接続パッド部に接続されて設けられている。
次に、この半導体装置の製造方法の一例について説明する。まず、図2に示すように、図1に示す配線2を形成するための配線形成用銅箔21の下面にポリイミドフィルム等からなる剥離層22が設けられ、剥離層22の下面に銅箔からなるベース板23が設けられたものを用意する。この場合、この用意したもののサイズは、図1に示す完成された半導体装置を複数個形成することが可能なサイズとなっている。そして、図2において、符号24で示す領域は個片化するための切断ラインに対応する領域である。
次に、図1に示す半導体装置の製造方法の他の例について説明する。この場合、図6に示す工程後に、図11に示すように、半導体構成体6の周囲における配線2を含む剥離層22の上面に、格子状の第1の封止材形成用シート25をピン等で位置決めしながら配置する。
図13はこの発明の第2実施形態としての半導体装置の断面図を示す。この半導体装置において、図1に示す半導体装置と異なる点は、半導体構成体6上に置ける封止材14の上面に銅箔からなる放熱層15を設け、放熱層15により、半導体基板7から発生する熱の放熱性を良くした点である。この場合、放熱層15は、例えば、図12に示す保護用銅箔27をフォトリソグラフィ法によりパターニングすると、形成することができるので、上側の加熱加圧板28の下面にエポキシ系樹脂等からなる熱硬化性樹脂が不要に付着するのを防止するための保護用銅箔27を有効に利用することができる。
図14はこの発明の第3実施形態としての半導体装置の断面図を示す。この半導体装置において、図1に示す半導体装置と大きく異なる点は、封止材14の上面に上層配線31を設け、上層配線31の一端部を半導体構成体6の周囲における封止材14中に設けられた上下導通部32を介して配線2の他端部上面に接続させた点である。
2 配線
3 表面処理層
4 開口部
5 半田ボール
6 半導体構成体
7 シリコン基板
8 接続パッド
9 絶縁膜
10 開口部
11 下地金属層
12 突起電極
13 アンダーフィル材
14 封止材
15 放熱層
21 配線形成用銅箔
22 剥離層
23 ベース板
24 切断ライン
25 第1の封止材形成用シート
26 第2の封止材形成用シート
27 保護用銅箔
31 上層配線
32 上下導通部
38 オーバーコート膜
41 第1の封止材形成用シート
42 第2の封止材形成用シート
43 第3の封止材形成用シート
44 上層配線形成用銅箔
Claims (22)
- 半導体基板および該半導体基板下に設けられた複数の外部接続用電極を有する半導体構成体と、前記半導体構成体のサイズよりも大きい領域の平面上に配置された複数の配線とを備えた半導体装置であって、前記半導体構成体は、その外部接続用電極が前記配線にボンディングされていることにより、前記配線上にフェースダウン方式により搭載され、前記半導体構成体と前記配線との間およびその周囲にアンダーフィル材がその下面が前記配線の下面と面一となるように設けられ、前記配線の配置領域よりも大きい領域において前記半導体構成体、前記アンダーフィル材および前記配線上に封止材がその下面が前記配線の下面と面一となるように設けられていることを特徴とする半導体装置。
- 請求項1に記載の発明において、前記配線、前記アンダーフィル材および前記封止材の下面に、前記配線の接続パッド部に対応する部分に開口部を有する下層絶縁膜が設けられていることを特徴とする半導体装置。
- 請求項2に記載の発明において、前記下層絶縁膜の開口部内およびその下方に半田ボールが前記配線の接続パッド部に接続されて設けられていることを特徴とする半導体装置。
- 請求項1〜3のいずれかに記載の発明において、前記封止材の上面に放熱層が設けられていることを特徴とする半導体装置。
- 請求項1〜3のいずれかに記載の発明において、前記封止材の上面に上層配線が前記半導体構成体の周囲における前記封止材中に設けられた上下導通部を介して前記配線に接続されて設けられていることを特徴とする半導体装置。
- 請求項5に記載の発明において、前記上層配線を含む前記封止材の上面にオーバーコート膜が設けられていることを特徴とする半導体装置。
- 請求項1〜3のいずれかに記載の発明において、前記配線は銅箔からなることを特徴とする半導体装置。
- 請求項1〜3のいずれかに記載の発明において、前記封止材は基材に熱硬化性樹脂を含浸させたものからなることを特徴とする半導体装置。
- 配線形成用銅箔の下面に剥離層およびベース板が設けられたものを用意する工程と、
前記配線形成用銅箔をパターニングして配線を形成する工程と、
半導体基板および該半導体基板下に設けられた複数の外部接続用電極を有する半導体構成体の外部接続用電極を前記配線にボンディングする工程と、
前記半導体構成体全体および前記配線の少なくとも一部を封止材で覆う工程と、
前記ベース板および前記剥離層を除去する工程と、
を有することを特徴とする半導体装置の製造方法。 - 請求項9に記載の発明において、前記半導体構成体と前記配線を含む前記剥離層との間にアンダーフィル材を形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項10に記載の発明において、前記ベース板および前記剥離層の除去により露出された前記配線、前記アンダーフィル材および前記封止材の下面に、前記配線の接続パッド部に対応する部分に開口部を有する下層絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項11に記載の発明において、前記下層絶縁膜を形成する工程後に、前記下層絶縁膜の開口部内およびその下方に半田ボールを前記配線の接続パッド部に接続させて形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項9〜12のいずれかに記載の発明において、前記封止材を形成する工程は、前記半導体構成体の周囲における前記配線を含む前記剥離層上に、前記半導体構成体に対応する部分に開口部を有する第1の封止材形成用シート、第2の封止材形成用シートおよび銅箔を配置し、上下から加熱加圧して、前記半導体構成体、前記アンダーフィル材および前記配線を含む前記剥離層上に封止材を形成し、且つ、前記封止材上に前記銅箔を固着する工程であることを特徴とする半導体装置の製造方法。
- 請求項13に記載の発明において、前記封止材上に固着された前記銅箔を除去する工程を有することを特徴とする半導体装置の製造方法。
- 請求項13に記載の発明において、前記封止材上に固着された前記銅箔により放熱層を形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項13に記載の発明において、前記第1、第2の封止材形成用シートは基材に熱硬化性樹脂を含浸させたものからなることを特徴とする半導体装置の製造方法。
- 請求項9〜12のいずれかに記載の発明において、前記封止材を形成する工程は、前記半導体構成体の周囲における前記配線を含む前記剥離層上に、前記半導体構成体に対応する部分に開口部を有する第1の封止材形成用シート、前記半導体構成体に対応する部分に開口部を有し且つ下側上下導通部を有する第2の封止材形成用シート、第3の封止材形成用シートおよび下面に上側上下導通部を有する上層配線形成用銅箔を配置し、上下から加熱加圧して、前記半導体構成体、前記アンダーフィル材および前記配線を含む前記剥離層上に封止材を形成し、且つ、前記半導体構成体の周囲における前記封止材中に前記下側上下導通部および前記上側上下導通部からなる上下導通部を形成し、さらに、前記封止材上に前記上層配線形成用銅箔を前記上下導通部を介して前記配線に接続させて固着する工程であることを特徴とする半導体装置の製造方法。
- 請求項17に記載の発明において、前記封止材上に固着された前記上層配線形成用銅箔をパターニングして上層配線を形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項18に記載の発明において、前記上層配線を含む前記封止材の上面にオーバーコート膜を形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項17に記載の発明において、前記第1、第2、第3の封止材形成用シートは基材に熱硬化性樹脂を含浸させたものからなることを特徴とする半導体装置の製造方法。
- 請求項9〜12のいずれかに記載の発明において、前記ベース板は銅箔からなることを特徴とする半導体装置の製造方法。
- 請求項21に記載の発明において、前記剥離層はポリイミドフィルムからなることを特徴とする半導体装置の製造方法。
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US7456493B2 (en) | 2005-04-15 | 2008-11-25 | Alps Electric Co., Ltd. | Structure for mounting semiconductor part in which bump and land portion are hardly detached from each other and method of manufacturing mounting substrate used therein |
-
2006
- 2006-11-28 JP JP2006319910A patent/JP4305502B2/ja not_active Expired - Fee Related
-
2007
- 2007-11-26 US US11/986,698 patent/US7790515B2/en not_active Expired - Fee Related
- 2007-11-27 TW TW096144880A patent/TWI371095B/zh not_active IP Right Cessation
- 2007-11-27 KR KR1020070121487A patent/KR100930156B1/ko active IP Right Grant
- 2007-11-28 CN CN2007101928794A patent/CN101192587B/zh active Active
Cited By (8)
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JP2012508374A (ja) * | 2008-11-10 | 2012-04-05 | イートン コーポレーション | 一体化されたシールプレートを有する圧力感知用モジュール及び圧力感知用モジュールを組み立てる方法 |
JP2010141132A (ja) * | 2008-12-11 | 2010-06-24 | Nitto Denko Corp | 半導体装置の製造方法 |
US8124457B2 (en) | 2008-12-11 | 2012-02-28 | Nitto Denko Corporation | Manufacturing method of transferring a wiring circuit layer on a metal support substrate to a semiconductor element |
US8895359B2 (en) | 2008-12-16 | 2014-11-25 | Panasonic Corporation | Semiconductor device, flip-chip mounting method and flip-chip mounting apparatus |
JP2011129767A (ja) * | 2009-12-18 | 2011-06-30 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
WO2015022808A1 (ja) * | 2013-08-13 | 2015-02-19 | 株式会社村田製作所 | 複合電子部品 |
JP2017055024A (ja) * | 2015-09-11 | 2017-03-16 | Shマテリアル株式会社 | 半導体素子実装用基板及び半導体装置、並びにそれらの製造方法 |
JPWO2017195517A1 (ja) * | 2016-05-09 | 2018-11-22 | 日立化成株式会社 | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US7790515B2 (en) | 2010-09-07 |
KR100930156B1 (ko) | 2009-12-07 |
TWI371095B (en) | 2012-08-21 |
TW200832649A (en) | 2008-08-01 |
JP4305502B2 (ja) | 2009-07-29 |
CN101192587A (zh) | 2008-06-04 |
US20080122087A1 (en) | 2008-05-29 |
CN101192587B (zh) | 2011-01-19 |
KR20080048411A (ko) | 2008-06-02 |
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