JP2007251145A - 積層パッケージ - Google Patents
積層パッケージ Download PDFInfo
- Publication number
- JP2007251145A JP2007251145A JP2007031205A JP2007031205A JP2007251145A JP 2007251145 A JP2007251145 A JP 2007251145A JP 2007031205 A JP2007031205 A JP 2007031205A JP 2007031205 A JP2007031205 A JP 2007031205A JP 2007251145 A JP2007251145 A JP 2007251145A
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- Prior art keywords
- rewiring
- stacked
- semiconductor chips
- printed circuit
- circuit board
- Prior art date
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B42—BOOKBINDING; ALBUMS; FILES; SPECIAL PRINTED MATTER
- B42D—BOOKS; BOOK COVERS; LOOSE LEAVES; PRINTED MATTER CHARACTERISED BY IDENTIFICATION OR SECURITY FEATURES; PRINTED MATTER OF SPECIAL FORMAT OR STYLE NOT OTHERWISE PROVIDED FOR; DEVICES FOR USE THEREWITH AND NOT OTHERWISE PROVIDED FOR; MOVABLE-STRIP WRITING OR READING APPARATUS
- B42D1/00—Books or other bound products
- B42D1/003—Books or other bound products characterised by shape or material of the sheets
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Abstract
【解決手段】上面にボンディングパッドと連結された第1再配線236と、内部に第1再配線と連結された貫通シリコンビア234と、下面に貫通シリコンビアと連結された第2再配線237とが具備された多数の半導体チップを、対応する第1再配線と第2再配線の間に第1はんだボール260aを介在させ積層された半導体チップと、最下部半導体チップ210の第1再配線と印刷回路基板400の電極端子の間に介在された第2はんだボール260bと、積層された半導体チップを含んだ印刷回路基板の上面を封止する封止材450と、及び印刷回路基板下面のボールランドに付着され実装手段として機能する第3はんだボール460cを含む。
【選択図】 図2B
Description
前記貫通シリコンビアは銅又はニッケル/金で成される。
前記貫通シリコンビアは半導体チップとの界面に形成された絶縁膜を含む。
210,220,230,310,410,420,430 半導体チップ
212,222,232,412,422,432 ボンディングパッド
214,224,234,414,424,434 貫通シリコンビア
216,226,236,416,426,436 第1再配線
217,227,237,417,427,437 第2再配線
218,418,428,438 はんだレジスト
250,450 封止材
260a,460a 第1はんだボール
260b,460b 第2はんだボール
260c,460c 第3はんだボール
360 はんだボール
Claims (9)
- 上面に配置される電極端子及び下面に配置されるボールランドを含んだ回路配線が形成された印刷回路基板と、
前記印刷回路基板上に少なくとも2つ以上がフェイスダウンタイプで積層され、上面にボンディングパッドと連結された第1再配線が具備され、内部に前記第1再配線と連結された貫通シリコンビアが具備され、下面に前記貫通シリコンビアと連結された第2再配線が具備された多数の半導体チップと、
前記積層された半導体チップの、対応する第1再配線と第2再配線の間に介在され相互間の電気的及び機械的連結を成す第1はんだボールと、
前記積層された半導体チップのうち最下部半導体チップの第1再配線と印刷回路基板の電極端子の間に介在され相互間の電気的及び機械的連結を成す第2はんだボールと、
前記積層された半導体チップを含んだ印刷回路基板の上面を封止する封止材と、
前記印刷回路基板下面のボールランドに付着され実装手段として機能する第3はんだボールと、
を含むことを特徴とする積層パッケージ。 - 前記第1再配線及び第2再配線は銅で形成されることを特徴とする請求項1に記載の積層パッケージ。
- 前記貫通シリコンビアは銅又はニッケル/金で形成されることを特徴とする請求項1に記載の積層パッケージ。
- 前記貫通シリコンビアは半導体チップとの界面に形成された絶縁膜を含むことを特徴とする請求項1に記載の積層パッケージ。
- 前記第1再配線及び第2再配線の一部分だけを露出させるように半導体チップの上面及び下面各々に形成されたはんだレジストをさらに含むことを特徴とする請求項1に記載の積層パッケージ。
- 前記半導体チップは互いに同一の大きさを有することを特徴とする請求項1に記載の積層パッケージ。
- 前記各半導体チップでの第1再配線及び第2再配線は同一の大きさで形成されることを特徴とする請求項6に記載の積層パッケージ。
- 前記半導体チップは互いに異なる大きさを有することを特徴とする請求項1に記載の積層パッケージ。
- 前記各半導体チップでの第2再配線は上部に配置される半導体チップの対応する第1再配線と連結可能な長さを有するように形成されることを特徴とする請求項8に記載の積層パッケージ。
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Also Published As
Publication number | Publication date |
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KR100753415B1 (ko) | 2007-08-30 |
TWI351092B (en) | 2011-10-21 |
CN100541789C (zh) | 2009-09-16 |
TW200737482A (en) | 2007-10-01 |
US20070222050A1 (en) | 2007-09-27 |
CN101038908A (zh) | 2007-09-19 |
US7598617B2 (en) | 2009-10-06 |
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