JP2007227550A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 140
- 238000004519 manufacturing process Methods 0.000 title abstract description 18
- 239000003351 stiffener Substances 0.000 claims abstract description 120
- 239000000758 substrate Substances 0.000 claims abstract description 88
- 229920005989 resin Polymers 0.000 claims abstract description 64
- 239000011347 resin Substances 0.000 claims abstract description 64
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims description 12
- 239000007769 metal material Substances 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 238000001816 cooling Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 230000002787 reinforcement Effects 0.000 description 4
- 229910001220 stainless steel Inorganic materials 0.000 description 4
- 239000010935 stainless steel Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000004382 potting Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
【解決手段】基板12と、この基板12にフリップチップ接合された半導体素子13と、基板12の半導体素子13の外周位置に配置された第1のスティフナ14と、基板上12の半導体素子13と第1のティフナ14との間に配設された補強樹脂15とを有する半導体装置において、補強樹脂15を補強する第2のスティフナ16を第2のスティフナ16内に配設する。
【選択図】図3
Description
基板と、
該基板に表面実装された半導体素子と、
前記基板の前記半導体素子の外周位置に配置された第1のスティフナと、
前記基板上の前記半導体素子と前記第1のティフナとの間に配設された補強樹脂とを有する半導体装置において、
前記補強樹脂を補強する第2のスティフナを配設したことを特徴とするものである。
請求項1記載の半導体装置において、
前記第2のスティフナは、金属材料であることを特徴とするものである。
請求項1又は2記載の半導体装置において、
前記第1のスティフナ及び第2のスティフナは、前記半導体素子の上面を外部に開放してなる構成であることを特徴とするものである。
請求項1乃至3のいずれか1項に記載の半導体装置において、
前記第2のスティフナは、前記基板から離間した構成であることを特徴とするものである。
基板に第1のスティフナを接着する工程と、
該第1のスティフナが接着された前記基板上に半導体素子を表面実装する工程と、
前記基板上の前記半導体素子と前記第1のスティフナとの間に補強用樹脂を形成する工程とを有し、
前記基板上の前記半導体素子と前記第1のスティフナとの間に前記補強用樹脂を形成する工程において、該補強用樹脂内に第2のスティフナを配設することを特徴とするものである。
尚、上記のフリップチップ接続に代えてワイヤボンディング接続を行うことも可能ではあるが、半導体装置10Aの薄型化を図る面からはフリップチップ接続の方が望ましい。
(付記1)
基板と、
該基板に表面実装された半導体素子と、
前記基板の前記半導体素子の外周位置に配置された第1のスティフナと、
前記基板上の前記半導体素子と前記第1のティフナとの間に配設された補強樹脂とを有する半導体装置において、
前記補強樹脂を補強する第2のスティフナを配設したことを特徴とする半導体装置。
(付記2)
前記第2のスティフナは、金属材料であることを特徴とする付記1記載の半導体装置。
(付記3)
前記第2のスティフナは、銅又はステンレスよりなることを特徴とする付記2記載の半導体装置。
(付記4)
前記第1のスティフナ及び第2のスティフナは、前記半導体素子の上面を外部に開放してなる構成であることを特徴とする付記1乃至3のいずれか1項に記載の半導体装置。
(付記5)
前記基板は、0,1mm以上0.5mm以下の厚さであることを特徴とする付記1乃至4のいずれか1項に記載の半導体装置。
(付記6)
前記第2のスティフナは、前記基板から離間した構成であることを特徴とする付記1乃至5のいずれか1項に記載の半導体装置。
(付記7)
基板に第1のスティフナを接着する工程と、
該第1のスティフナが接着された前記基板上に半導体素子を表面実装する工程と、
前記基板上の前記半導体素子と前記第1のスティフナとの間に補強用樹脂を形成する工程とを有し、
前記基板上の前記半導体素子と前記第1のスティフナとの間に前記補強用樹脂を形成する工程において、該補強用樹脂内に第2のスティフナを配設することを特徴とする半導体装置の製造方法。
(付記8)
前記基板上の前記半導体素子と前記第1のスティフナとの間に先ず前記補強用樹脂を配設し、該補強用樹脂内に第2のスティフナを配設し、その後に前記補強用樹脂を硬化させることを特徴とする半導体装置の製造方法。
12 基板
13 半導体素子
14 第1のスティフナ
15 補強樹脂
16 第2のスティフナ
19 アンダーフィルレジン
20 第2のスティフナ
20a 面取り部
Claims (5)
- 基板と、
該基板に表面実装された半導体素子と、
前記基板の前記半導体素子の外周位置に配置された第1のスティフナと、
前記基板上の前記半導体素子と前記第1のティフナとの間に配設された補強樹脂とを有する半導体装置において、
前記補強樹脂を補強する第2のスティフナを配設したことを特徴とする半導体装置。 - 前記第2のスティフナは、金属材料であることを特徴とする請求項1記載の半導体装置。
- 前記第1のスティフナ及び第2のスティフナは、前記半導体素子の上面を外部に開放してなる構成であることを特徴とする請求項1又は2記載の半導体装置。
- 前記第2のスティフナは、前記基板から離間した構成であることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 基板に第1のスティフナを接着する工程と、
該第1のスティフナが接着された前記基板上に半導体素子を表面実装する工程と、
前記基板上の前記半導体素子と前記第1のスティフナとの間に補強用樹脂を形成する工程とを有し、
前記基板上の前記半導体素子と前記第1のスティフナとの間に前記補強用樹脂を形成する工程において、該補強用樹脂内に第2のスティフナを配設することを特徴とする半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2006045625A JP4714598B2 (ja) | 2006-02-22 | 2006-02-22 | 半導体装置及びその製造方法 |
US11/488,640 US8004096B2 (en) | 2006-02-22 | 2006-07-19 | Semiconductor device and a manufacturing method thereof |
TW095126361A TWI318442B (en) | 2006-02-22 | 2006-07-19 | A semiconductor device and a manufacturing method thereof |
CNB2006101095856A CN100530613C (zh) | 2006-02-22 | 2006-08-14 | 半导体器件及其制造方法 |
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JP2006045625A JP4714598B2 (ja) | 2006-02-22 | 2006-02-22 | 半導体装置及びその製造方法 |
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JP2007227550A true JP2007227550A (ja) | 2007-09-06 |
JP4714598B2 JP4714598B2 (ja) | 2011-06-29 |
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US (1) | US8004096B2 (ja) |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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DE102010024119A1 (de) | 2009-07-07 | 2011-01-13 | Fujitsu Ltd., Kawasaki | Halbleitervorrichtung, Herstellungsverfahren einer Halbleitervorrichtung und elektronisches Gerät |
JP2011526422A (ja) * | 2008-07-02 | 2011-10-06 | シーメンス アクチエンゲゼルシヤフト | 高温で使用するためのプレーナ型電力電子構成素子およびその製造方法 |
WO2012029526A1 (ja) * | 2010-08-30 | 2012-03-08 | 住友ベークライト株式会社 | 半導体パッケージおよび半導体装置 |
JP2016115929A (ja) * | 2014-12-16 | 2016-06-23 | インテル・コーポレーション | マイクロ電子パッケージ用ピクチャフレームスティフナ |
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Publication number | Priority date | Publication date | Assignee | Title |
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TWI311366B (en) * | 2006-06-30 | 2009-06-21 | Advanced Semiconductor Eng | A flip-chip package structure with stiffener |
JP5085081B2 (ja) * | 2006-09-22 | 2012-11-28 | パナソニック株式会社 | 電子部品実装構造体 |
US8247900B2 (en) * | 2009-12-29 | 2012-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Flip chip package having enhanced thermal and mechanical performance |
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JP5879030B2 (ja) * | 2010-11-16 | 2016-03-08 | 新光電気工業株式会社 | 電子部品パッケージ及びその製造方法 |
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Also Published As
Publication number | Publication date |
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US8004096B2 (en) | 2011-08-23 |
CN100530613C (zh) | 2009-08-19 |
TW200733315A (en) | 2007-09-01 |
CN101026131A (zh) | 2007-08-29 |
US20070194464A1 (en) | 2007-08-23 |
JP4714598B2 (ja) | 2011-06-29 |
TWI318442B (en) | 2009-12-11 |
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