JP2009135428A - 実装構造体とその製造方法 - Google Patents
実装構造体とその製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229920005989 resin Polymers 0.000 claims abstract description 86
- 239000011347 resin Substances 0.000 claims abstract description 86
- 230000002093 peripheral effect Effects 0.000 claims description 39
- 239000004020 conductor Substances 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 description 32
- 239000000758 substrate Substances 0.000 description 18
- 229910000679 solder Inorganic materials 0.000 description 16
- 230000007480 spreading Effects 0.000 description 8
- 238000003892 spreading Methods 0.000 description 8
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10719—Land grid array [LGA]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】少なくとも第1の面1Aに電子部品4が実装された配線基板1と、少なくとも電子部品4と配線基板1間に設けられた樹脂3と、配線基板1の電子部品4の実装位置に対応する領域に設けられた貫通孔2と、を備え、電子部品4の実装位置に対応する領域の周辺で、少なくとも電子部品4と重なるように配線基板1に凸部20を設けた構成を有する。
【選択図】図1
Description
図1(a)は、本発明の実施の形態1における実装構造体の構成を示す外観斜視図で、図1(b)は図1(a)の1B−1B線断面図である。図2(a)は本発明の実施の形態1における実装構造体を構成する配線基板を説明する外観斜視図で、図2(b)は図2(a)の配線基板の絶縁膜を除いた状態の平面図である。
図6(a)は、本発明の実施の形態2における実装構造体の構成を示す外観斜視図で、図6(b)は図6(a)の6B−6B線断面図である。
図9(a)は、本発明の実施の形態3における実装構造体の構成を示す外観斜視図で、図9(b)は図9(a)の9B−9B線断面図である。
1A,31A 第1の面
1B,31B 第2の面
2 貫通孔
3,103 樹脂
4 電子部品(第1電子部品)
5,105 はんだ
6,106 パッド
7,71,72,73,74,75,107,171 絶縁膜
8,108 ディスペンサー
9 領域
10,30,80 実装構造体
20,20A 凸部(第1凸部)
22A 曲線部
22B 平坦部
40 第2電子部品
50,50A 第2凸部
61,161 配線パターン
62,64 周辺導体部
104 半導体チップ
109 充填されない空間
110 充填されない領域
Claims (11)
- 少なくとも第1の面に電子部品が実装された配線基板と、
少なくとも前記電子部品と前記配線基板間に設けられた樹脂と、
前記配線基板の前記電子部品の実装位置に対応する領域に設けられた貫通孔と、を備え、
前記電子部品の実装位置に対応する領域の周辺で、少なくとも前記電子部品と重なるように前記配線基板に凸部が設けられていることを特徴とする実装構造体。 - 前記電子部品を第1電子部品とし、前記凸部を第1凸部として、
前記配線基板の前記第1の面と対向する第2の面に第2電子部品を実装し、前記第2電子部品と前記配線基板間に設けられた樹脂とともに、前記第2電子部品の実装位置に対応する領域の周辺に設けられ、少なくとも前記第2電子部品と重なるように前記配線基板に第2凸部がさらに設けられていることを特徴とする請求項1に記載の実装構造体。 - 前記凸部は、前記配線基板に設けられた周辺導体部と、前記周辺導体部を被覆する絶縁膜から構成されていることを特徴とする請求項1に記載の実装構造体。
- 前記周辺導体部が、前記配線基板の前記電子部品を接続するパッドまたは配線パターンと同時に形成されていることを特徴とする請求項3に記載の実装構造体。
- 前記凸部が4角形の枠状であることを特徴とする請求項1に記載の実装構造体。
- 前記4角形の枠状の少なくとも内周側の角部が曲線状に設けられていることを特徴とする請求項5に記載の実装構造体。
- 前記4角形の枠状の少なくとも内周側の角部が平坦化されていることを特徴とする請求項5に記載の実装構造体。
- 前記凸部が、階段状の断面形状を有することを特徴とする請求項1に記載の実装構造体。
- 配線基板の少なくとも第1の面に電子部品の実装位置に対応する領域で前記電子部品の周辺と重なる枠状の凸部と前記領域内に貫通孔とを形成するステップと、
前記領域に前記電子部品を実装するステップと、
前記電子部品と前記配線基板間に前記凸部と前記電子部品の間隙から樹脂を注入するステップと、
前記樹脂を熱処理するステップと、
を含むことを特徴とする実装構造体の製造方法。 - 前記電子部品を第1電子部品とし、前記凸部を第1凸部として、
配線基板の第1の面と対向する第2の面に第2電子部品の実装位置に対応する領域で前記第2電子部品の周辺と重なる枠状の第2凸部を前記領域内に形成するステップと、
前記領域に前記第2電子部品を実装するステップと、
前記第2電子部品と前記配線基板間に前記第2凸部と前記第2電子部品の間隙から樹脂を注入するステップと、
をさらに含むことを特徴とする請求項9に記載の実装構造体の製造方法。 - 前記樹脂を前記配線基板の前記凸部の1箇所のみから注入することを特徴とする請求項9に記載の実装構造体の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008245816A JP5353153B2 (ja) | 2007-11-09 | 2008-09-25 | 実装構造体 |
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JP2007291504 | 2007-11-09 | ||
JP2007291504 | 2007-11-09 | ||
JP2008245816A JP5353153B2 (ja) | 2007-11-09 | 2008-09-25 | 実装構造体 |
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JP2009135428A true JP2009135428A (ja) | 2009-06-18 |
JP5353153B2 JP5353153B2 (ja) | 2013-11-27 |
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JP2008245816A Expired - Fee Related JP5353153B2 (ja) | 2007-11-09 | 2008-09-25 | 実装構造体 |
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US (1) | US8179686B2 (ja) |
JP (1) | JP5353153B2 (ja) |
CN (1) | CN101431061B (ja) |
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CN101890605B (zh) * | 2010-07-08 | 2014-01-08 | 株洲南车时代电气股份有限公司 | 一种功率半导体芯片焊接装置 |
JP2012134400A (ja) * | 2010-12-23 | 2012-07-12 | Denso Corp | 回路基板 |
TWI467757B (zh) * | 2013-08-02 | 2015-01-01 | Chipbond Technology Corp | 半導體結構 |
JP2016149384A (ja) * | 2015-02-10 | 2016-08-18 | パナソニックIpマネジメント株式会社 | 部品実装装置および部品実装方法ならびに部品実装ライン |
JP2016149383A (ja) * | 2015-02-10 | 2016-08-18 | パナソニックIpマネジメント株式会社 | 部品実装装置および部品実装方法ならびに部品実装ライン |
KR20230023834A (ko) * | 2020-12-09 | 2023-02-20 | 주식회사 솔루엠 | 에어포켓 방지 기판, 에어포켓 방지 기판 모듈, 이를 포함하는 전기기기 및 이를 포함하는 전기기기의 제조 방법 |
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US20090120675A1 (en) | 2009-05-14 |
CN101431061B (zh) | 2010-12-22 |
JP5353153B2 (ja) | 2013-11-27 |
US8179686B2 (en) | 2012-05-15 |
CN101431061A (zh) | 2009-05-13 |
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